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[PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u |
Date: |
Thu, 6 Apr 2023 15:03:44 -0300 |
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 9 ++++-----
target/riscv/cpu.h | 1 -
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cded82ac7a..9565495839 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
- cpu->cfg.ext_u = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@@ -842,7 +841,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
- if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
+ if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
@@ -1170,7 +1169,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVS)) {
ext |= RVS;
}
- if (riscv_cpu_cfg(env)->ext_u) {
+ if (riscv_has_ext(env, RVU)) {
ext |= RVU;
}
if (riscv_cpu_cfg(env)->ext_h) {
@@ -1508,6 +1507,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVM, .enabled = true},
{.name = "s", .description = "Supervisor-level instructions",
.misa_bit = RVS, .enabled = true},
+ {.name = "u", .description = "User-level instructions",
+ .misa_bit = RVU, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1531,7 +1532,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
@@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b8e541e5f..486061589e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_u;
bool ext_h;
bool ext_j;
bool ext_v;
--
2.39.2
- [PATCH v4 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data, (continued)
- [PATCH v4 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 04/20] target/riscv: introduce riscv_cpu_add_misa_properties(), Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 05/20] target/riscv: remove cpu->cfg.ext_a, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 06/20] target/riscv: remove cpu->cfg.ext_c, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 07/20] target/riscv: remove cpu->cfg.ext_d, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 08/20] target/riscv: remove cpu->cfg.ext_f, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 09/20] target/riscv: remove cpu->cfg.ext_i, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 10/20] target/riscv: remove cpu->cfg.ext_e, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 11/20] target/riscv: remove cpu->cfg.ext_m, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 12/20] target/riscv: remove cpu->cfg.ext_s, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u,
Daniel Henrique Barboza <=
- [PATCH v4 14/20] target/riscv: remove cpu->cfg.ext_h, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 15/20] target/riscv: remove cpu->cfg.ext_j, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 16/20] target/riscv: remove cpu->cfg.ext_v, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g, Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg(), Daniel Henrique Barboza, 2023/04/06
- [PATCH v4 20/20] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/04/06
- Re: [PATCH v4 00/20] remove MISA ext_N flags from cpu->cfg, Alistair Francis, 2023/04/10