Re: [PATCH v3 16/20] target/riscv: remove cpu->cfg.ext_v

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Create a new "v" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
> replaced with riscv_has_ext(env, RVV).
>
> Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 12 +++++-------
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 86edc08545..b40a55bc8d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -876,7 +876,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>      }
>
>      /* The V vector extension depends on the Zve64d extension */
> -    if (cpu->cfg.ext_v) {
> +    if (riscv_has_ext(env, RVV)) {
>          cpu->cfg.ext_zve64d = true;
>      }
>
> @@ -958,7 +958,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          cpu->cfg.ext_zksh = true;
>      }
>
> -    if (cpu->cfg.ext_v) {
> +    if (riscv_has_ext(env, RVV)) {
>          int vext_version = VEXT_VERSION_1_00_0;
>          if (!is_power_of_2(cpu->cfg.vlen)) {
>              error_setg(errp,
> @@ -1115,7 +1115,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>      if (riscv_has_ext(env, RVH)) {
>          ext |= RVH;
>      }
> -    if (riscv_cpu_cfg(env)->ext_v) {
> +    if (riscv_has_ext(env, RVV)) {
>          ext |= RVV;
>      }
>      if (riscv_has_ext(env, RVJ)) {
> @@ -1453,6 +1453,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>       .misa_bit = RVH, .enabled = true},
>      {.name = "x-j", .description = "Dynamic translated languages",
>       .misa_bit = RVJ, .enabled = false},
> +    {.name = "v", .description = "Vector operations",
> +     .misa_bit = RVV, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1476,7 +1478,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>      /* Defaults for standard extensions */
>      DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -    DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>      DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
>      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> @@ -1569,7 +1570,6 @@ static Property riscv_cpu_extensions[] = {
>  static void register_cpu_props(Object *obj)
>  {
>      RISCVCPU *cpu = RISCV_CPU(obj);
> -    uint32_t misa_ext = cpu->env.misa_ext;
>      Property *prop;
>      DeviceState *dev = DEVICE(obj);
>
> @@ -1579,8 +1579,6 @@ static void register_cpu_props(Object *obj)
>       * later on.
>       */
>      if (cpu->env.misa_ext != 0) {
> -        cpu->cfg.ext_v = misa_ext & RVV;
> -
>          /*
>           * We don't want to set the default riscv_cpu_extensions
>           * in this case.
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 43a40ba950..c0280ace2a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>      bool ext_g;
> -    bool ext_v;
>      bool ext_zba;
>      bool ext_zbb;
>      bool ext_zbc;
> --
> 2.39.2
>
>