Re: [PATCH v3 15/20] target/riscv: remove cpu->cfg.ext_j

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Create a new "j" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
> replaced with riscv_has_ext(env, RVJ).
>
> Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 6 +++---
>  target/riscv/cpu.h | 1 -
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 76dcf26f6c..86edc08545 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1118,7 +1118,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>      if (riscv_cpu_cfg(env)->ext_v) {
>          ext |= RVV;
>      }
> -    if (riscv_cpu_cfg(env)->ext_j) {
> +    if (riscv_has_ext(env, RVJ)) {
>          ext |= RVJ;
>      }
>
> @@ -1451,6 +1451,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>       .misa_bit = RVU, .enabled = true},
>      {.name = "h", .description = "Hypervisor",
>       .misa_bit = RVH, .enabled = true},
> +    {.name = "x-j", .description = "Dynamic translated languages",
> +     .misa_bit = RVJ, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1547,7 +1549,6 @@ static Property riscv_cpu_extensions[] = {
>
>      /* These are experimental so mark with 'x-' */
>      DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
> -    DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>      /* ePMP 0.9.3 */
>      DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>      DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> @@ -1579,7 +1580,6 @@ static void register_cpu_props(Object *obj)
>       */
>      if (cpu->env.misa_ext != 0) {
>          cpu->cfg.ext_v = misa_ext & RVV;
> -        cpu->cfg.ext_j = misa_ext & RVJ;
>
>          /*
>           * We don't want to set the default riscv_cpu_extensions
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index f3cb28443c..43a40ba950 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>      bool ext_g;
> -    bool ext_j;
>      bool ext_v;
>      bool ext_zba;
>      bool ext_zbb;
> --
> 2.39.2
>
>