[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 2/6] target/riscv: Update cur_pmmask/base when xl changes
From: |
Alistair Francis |
Subject: |
Re: [PATCH v6 2/6] target/riscv: Update cur_pmmask/base when xl changes |
Date: |
Wed, 5 Apr 2023 14:38:53 +1000 |
On Tue, Apr 4, 2023 at 12:08 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> write_mstatus() can only change current xl when in debug mode.
> And we need update cur_pmmask/base in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..43b9ad4500 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState
> *env, int csrno,
> mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
> }
> env->mstatus = mstatus;
> - env->xl = cpu_recompute_xl(env);
>
> + /*
> + * Except in debug mode, UXL/SXL can only be modified by higher
> + * privilege mode. So xl will not be changed in normal mode.
> + */
> + if (env->debugger) {
> + env->xl = cpu_recompute_xl(env);
> + riscv_cpu_update_mask(env);
> + }
> return RISCV_EXCP_NONE;
> }
>
> --
> 2.25.1
>
>
- [PATCH v6 0/6] target/riscv: Fix pointer mask related support, Weiwei Li, 2023/04/03
- [PATCH v6 5/6] target/riscv: Enable PC-relative translation in system mode, Weiwei Li, 2023/04/03
- [PATCH v6 2/6] target/riscv: Update cur_pmmask/base when xl changes, Weiwei Li, 2023/04/03
- Re: [PATCH v6 2/6] target/riscv: Update cur_pmmask/base when xl changes,
Alistair Francis <=
- [PATCH v6 3/6] target/riscv: Fix target address to update badaddr, Weiwei Li, 2023/04/03
- [PATCH v6 1/6] target/riscv: Fix pointer mask transformation for vector address, Weiwei Li, 2023/04/03
- [PATCH v6 6/6] target/riscv: Add pointer mask support for instruction fetch, Weiwei Li, 2023/04/03
- [PATCH v6 4/6] target/riscv: Add support for PC-relative translation, Weiwei Li, 2023/04/03