Re: [RFC PATCH v2 38/44] target/loongarch: Implement vbitsel vset

[Richard Henderson]

On 3/27/23 20:06, Song Gao wrote:
> +static void gen_vbitseli(unsigned vece, TCGv_vec a, TCGv_vec b, int64_t imm)
> +{
> +    TCGv_vec t;
> +
> +    t = tcg_temp_new_vec_matching(a);
> +    tcg_gen_dupi_vec(vece, t, imm);

tcg_constant_vec_matching.

> +void HELPER(vseteqz_v)(CPULoongArchState *env, uint32_t cd, uint32_t vj)
> +{
> +    VReg *Vj = &(env->fpr[vj].vreg);
> +    env->cf[cd & 0x7] = (Vj->Q(0) == 0);
> +}
> +
> +void HELPER(vsetnez_v)(CPULoongArchState *env, uint32_t cd, uint32_t vj)
> +{
> +    VReg *Vj = &(env->fpr[vj].vreg);
> +    env->cf[cd & 0x7] = (Vj->Q(0) != 0);
> +}

This is trivial inline.

> +#define SETANYEQZ(NAME, BIT, E)                                     \
> +void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t vj) \
> +{                                                                   \
> +    int i;                                                          \
> +    bool ret = false;                                               \
> +    VReg *Vj = &(env->fpr[vj].vreg);                                \
> +                                                                    \
> +    for (i = 0; i < LSX_LEN/BIT; i++) {                             \
> +        ret |= (Vj->E(i) == 0);                                     \
> +    }                                                               \
> +    env->cf[cd & 0x7] = ret;                                        \
> +}
> +SETANYEQZ(vsetanyeqz_b, 8, B)
> +SETANYEQZ(vsetanyeqz_h, 16, H)
> +SETANYEQZ(vsetanyeqz_w, 32, W)
> +SETANYEQZ(vsetanyeqz_d, 64, D)

These could be inlined, though slightly harder.
C.f. target/arm/sve_helper.c, do_match2 (your n == 0).

Anyway, leaving this as-is for now is also ok.


r~