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[PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execut
From: |
Lawrence Hunter |
Subject: |
[PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support |
Date: |
Fri, 10 Mar 2023 09:11:43 +0000 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
target/riscv/helper.h | 4 ++++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 +
target/riscv/vcrypto_helper.c | 11 +++++++++++
4 files changed, 17 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 625f9872d0..b4baa22692 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1169,6 +1169,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 87473a77c0..bdefcd3fa2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -922,3 +922,4 @@ vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
+vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc
b/target/riscv/insn_trans/trans_rvzvkb.c.inc
index 7cd114ae71..77ba8bc713 100644
--- a/target/riscv/insn_trans/trans_rvzvkb.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc
@@ -183,3 +183,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a)
}
GEN_OPIV_TRANS(vbrev8_v, vxrev8_check)
+GEN_OPIV_TRANS(vrev8_v, vxrev8_check)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 5d2a995de6..ecf21c50f8 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/bitops.h"
+#include "qemu/bswap.h"
#include "cpu.h"
#include "exec/memop.h"
#include "exec/exec-all.h"
@@ -114,3 +115,13 @@ GEN_VEXT_V(vbrev8_v_b, 1)
GEN_VEXT_V(vbrev8_v_h, 2)
GEN_VEXT_V(vbrev8_v_w, 4)
GEN_VEXT_V(vbrev8_v_d, 8)
+
+#define DO_IDENTITY(a) (a)
+RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY)
+RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16)
+RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32)
+RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64)
+GEN_VEXT_V(vrev8_v_b, 1)
+GEN_VEXT_V(vrev8_v_h, 2)
+GEN_VEXT_V(vrev8_v_w, 4)
+GEN_VEXT_V(vrev8_v_d, 8)
--
2.39.2
- [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality, (continued)
- [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 09/45] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/03/10
- [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 01/45] target/riscv: Add zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support,
Lawrence Hunter <=
- [PATCH 16/45] target/riscv: Add zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 15/45] target/riscv: Expose zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10