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[PATCH 09/45] qemu/bitops.h: Limit rotate amounts
From: |
Lawrence Hunter |
Subject: |
[PATCH 09/45] qemu/bitops.h: Limit rotate amounts |
Date: |
Fri, 10 Mar 2023 09:11:39 +0000 |
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
---
include/qemu/bitops.h | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..c443995b3b 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,8 @@ static inline unsigned long find_first_zero_bit(const
unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ shift &= 7;
+ return (word << shift) | (word >> (8 - shift));
}
/**
@@ -228,7 +229,8 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ shift &= 7;
+ return (word >> shift) | (word << (8 - shift));
}
/**
@@ -238,7 +240,8 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ shift &= 15;
+ return (word << shift) | (word >> (16 - shift));
}
/**
@@ -248,7 +251,8 @@ static inline uint16_t rol16(uint16_t word, unsigned int
shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ shift &= 15;
+ return (word >> shift) | (word << (16 - shift));
}
/**
@@ -258,7 +262,8 @@ static inline uint16_t ror16(uint16_t word, unsigned int
shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ shift &= 31;
+ return (word << shift) | (word >> (32 - shift));
}
/**
@@ -268,7 +273,8 @@ static inline uint32_t rol32(uint32_t word, unsigned int
shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ shift &= 31;
+ return (word >> shift) | (word << (32 - shift));
}
/**
@@ -278,7 +284,8 @@ static inline uint32_t ror32(uint32_t word, unsigned int
shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ shift &= 63;
+ return (word << shift) | (word >> (64 - shift));
}
/**
@@ -288,7 +295,8 @@ static inline uint64_t rol64(uint64_t word, unsigned int
shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ shift &= 63;
+ return (word >> shift) | (word << (64 - shift));
}
/**
--
2.39.2
- [PATCH 00/45] Add RISC-V vector cryptographic instruction set support, Lawrence Hunter, 2023/03/10
- [PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 09/45] qemu/bitops.h: Limit rotate amounts,
Lawrence Hunter <=
- [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 01/45] target/riscv: Add zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 16/45] target/riscv: Add zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support, Lawrence Hunter, 2023/03/10