[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg
From: |
Richard Henderson |
Subject: |
[PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg |
Date: |
Thu, 9 Mar 2023 12:05:05 -0800 |
Tidy up the whole function, hoisting is_bfffo as a common test
for whether tlen and tofs needed. Use tcg_constant_i32, and load
a separate temporary for mask.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 42 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0002d80bf9..e78722fba8 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4027,14 +4027,8 @@ DISAS_INSN(bfop_reg)
TCGv src = DREG(insn, 0);
int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
int ofs = extract32(ext, 6, 5); /* big bit-endian */
- TCGv mask, tofs, tlen;
-
- tofs = NULL;
- tlen = NULL;
- if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
- tofs = tcg_temp_new();
- tlen = tcg_temp_new();
- }
+ TCGv mask, tofs = NULL, tlen = NULL;
+ bool is_bfffo = (insn & 0x0f00) == 0x0d00;
if ((ext & 0x820) == 0) {
/* Immediate width and offset. */
@@ -4045,45 +4039,49 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
}
tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
- mask = tcg_const_i32(ror32(maski, ofs));
- if (tofs) {
- tcg_gen_movi_i32(tofs, ofs);
- tcg_gen_movi_i32(tlen, len);
+
+ mask = tcg_constant_i32(ror32(maski, ofs));
+ if (is_bfffo) {
+ tofs = tcg_constant_i32(ofs);
+ tlen = tcg_constant_i32(len);
}
} else {
TCGv tmp = tcg_temp_new();
+
+ mask = tcg_temp_new();
if (ext & 0x20) {
/* Variable width */
tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
tcg_gen_andi_i32(tmp, tmp, 31);
- mask = tcg_const_i32(0x7fffffffu);
- tcg_gen_shr_i32(mask, mask, tmp);
- if (tlen) {
+ tcg_gen_shr_i32(mask, tcg_constant_i32(0x7fffffffu), tmp);
+ if (is_bfffo) {
+ tlen = tcg_temp_new();
tcg_gen_addi_i32(tlen, tmp, 1);
}
} else {
/* Immediate width */
- mask = tcg_const_i32(0x7fffffffu >> (len - 1));
- if (tlen) {
- tcg_gen_movi_i32(tlen, len);
+ tcg_gen_movi_i32(mask, 0x7fffffffu >> (len - 1));
+ if (is_bfffo) {
+ tlen = tcg_constant_i32(len);
}
}
+
if (ext & 0x800) {
/* Variable offset */
tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotr_i32(mask, mask, tmp);
- if (tofs) {
- tcg_gen_mov_i32(tofs, tmp);
+ if (is_bfffo) {
+ tofs = tmp;
}
} else {
/* Immediate offset (and variable width) */
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotri_i32(mask, mask, ofs);
- if (tofs) {
- tcg_gen_movi_i32(tofs, ofs);
+ if (is_bfffo) {
+ tofs = tcg_constant_i32(ofs);
}
}
}
--
2.34.1
- [PULL v2 36/91] target/tricore: Remove `NB_MMU_MODES` define, (continued)
- [PULL v2 36/91] target/tricore: Remove `NB_MMU_MODES` define, Richard Henderson, 2023/03/09
- [PULL v2 37/91] target/xtensa: Remove `NB_MMU_MODES` define, Richard Henderson, 2023/03/09
- [PULL v2 35/91] target/sparc: Remove `NB_MMU_MODES` define, Richard Henderson, 2023/03/09
- [PULL v2 38/91] include/exec: Remove guards around `NB_MMU_MODES`, Richard Henderson, 2023/03/09
- [PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS, Richard Henderson, 2023/03/09
- [PULL v2 40/91] target/avr: Avoid use of tcg_const_i32 throughout, Richard Henderson, 2023/03/09
- [PULL v2 41/91] target/cris: Avoid use of tcg_const_i32 throughout, Richard Henderson, 2023/03/09
- [PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f, Richard Henderson, 2023/03/09
- [PULL v2 43/91] target/hppa: Avoid use of tcg_const_i32 throughout, Richard Henderson, 2023/03/09
- [PULL v2 45/91] target/m68k: Avoid tcg_const_i32 when modified, Richard Henderson, 2023/03/09
- [PULL v2 46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg,
Richard Henderson <=
- [PULL v2 44/91] target/i386: Avoid use of tcg_const_* throughout, Richard Henderson, 2023/03/09
- [PULL v2 48/91] target/mips: Split out gen_lxl, Richard Henderson, 2023/03/09
- [PULL v2 47/91] target/m68k: Avoid tcg_const_* throughout, Richard Henderson, 2023/03/09
- [PULL v2 49/91] target/mips: Split out gen_lxr, Richard Henderson, 2023/03/09
- [PULL v2 52/91] target/ppc: Split out gen_vx_vmul10, Richard Henderson, 2023/03/09
- [PULL v2 50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld, Richard Henderson, 2023/03/09
- [PULL v2 54/91] target/rx: Use tcg_gen_abs_i32, Richard Henderson, 2023/03/09
- [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation, Richard Henderson, 2023/03/09
- [PULL v2 51/91] target/mips: Avoid tcg_const_* throughout, Richard Henderson, 2023/03/09
- [PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad, Richard Henderson, 2023/03/09