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Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0 |
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Date: |
Fri, 3 Mar 2023 12:20:44 +0000 |
On Fri, 3 Mar 2023 at 08:41, Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> merged tag 'buildsys-qom-qdev-ui-20230227'
> The following changes since commit 627634031092e1514f363fd8659a579398de0f0e:
>
> Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu
> into staging (2023-02-28 15:09:18 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303
>
> for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c:
>
> Merge patch series "target/riscv: some vector_helper.c cleanups"
> (2023-03-01 18:09:48 -0800)
>
> ----------------------------------------------------------------
> Fifth RISC-V PR for QEMU 8.0
>
> * Experimantal support for writable misa.
> * Support for Svadu extension.
> * Support for the Zicond extension.
> * Fixes to gdbstub, CSR accesses, dependencies between the various
> floating-point exceptions, and XTheadMemPair.
> * Many cleanups.
>
> ----------------------------------------------------------------
> There's a lot of cleanups here, a handful of which ended up stepping on
> each other and were necessary for various features. I tried to keep
> each individual patch set intact, but that led to some merge conflicts
> and a bit of a clunky history -- I'm not sure what the right answer is
> there, happy to re-spin this to be more linear if that's problem for
> folks.
It looks like in this case you got lucky, but in general I don't
recommend including merge commits in your pull requests, rather
than fixing up patches by rebasing them. If I find that a
pull request has merge conflicts when I try to merge it, I'm
going to kick it back to you to rebase, and then you need to
rebase and fix up the commits in it anyway...
thanks
-- PMM
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, (continued)
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr(), Palmer Dabbelt, 2023/03/03
- [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s(), Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Palmer Dabbelt, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0,
Peter Maydell <=
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03