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[PATCH v8 20/23] hw/isa/piix: Rename functions to be shared for interrup
From: |
Bernhard Beschow |
Subject: |
[PATCH v8 20/23] hw/isa/piix: Rename functions to be shared for interrupt triggering |
Date: |
Thu, 2 Mar 2023 22:21:58 +0100 |
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-40-shentey@gmail.com>
---
hw/isa/piix.c | 56 +++++++++++++++++++++++++--------------------------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 8206cbebf3..d6c39d6f37 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -41,47 +41,47 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
-static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
+static void piix_set_irq_pic(PIIXState *piix, int pic_irq)
{
- qemu_set_irq(piix3->pic[pic_irq],
- !!(piix3->pic_levels &
+ qemu_set_irq(piix->pic[pic_irq],
+ !!(piix->pic_levels &
(((1ULL << PIIX_NUM_PIRQS) - 1) <<
(pic_irq * PIIX_NUM_PIRQS))));
}
-static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
+static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int level)
{
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ pic_irq = piix->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
- piix3->pic_levels &= ~mask;
- piix3->pic_levels |= mask * !!level;
+ piix->pic_levels &= ~mask;
+ piix->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
+static void piix_set_irq_level(PIIXState *piix, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ pic_irq = piix->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
- piix3_set_irq_level_internal(piix3, pirq, level);
+ piix_set_irq_level_internal(piix, pirq, level);
- piix3_set_irq_pic(piix3, pic_irq);
+ piix_set_irq_pic(piix, pic_irq);
}
-static void piix3_set_irq(void *opaque, int pirq, int level)
+static void piix_set_irq(void *opaque, int pirq, int level)
{
- PIIXState *piix3 = opaque;
- piix3_set_irq_level(piix3, pirq, level);
+ PIIXState *piix = opaque;
+ piix_set_irq_level(piix, pirq, level);
}
static void piix4_set_irq(void *opaque, int irq_num, int level)
@@ -122,29 +122,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void
*opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIXState *piix3)
+static void piix_update_irq_levels(PIIXState *piix)
{
- PCIBus *bus = pci_get_bus(&piix3->dev);
+ PCIBus *bus = pci_get_bus(&piix->dev);
int pirq;
- piix3->pic_levels = 0;
+ piix->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+ piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq));
}
}
-static void piix3_write_config(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
+static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val,
+ int len)
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
+ PIIXState *piix = PIIX_PCI_DEVICE(dev);
int pic_irq;
- pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
- piix3_update_irq_levels(piix3);
+ pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev));
+ piix_update_irq_levels(piix);
for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
- piix3_set_irq_pic(piix3, pic_irq);
+ piix_set_irq_pic(piix, pic_irq);
}
}
}
@@ -166,7 +166,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
}
}
- piix3_write_config(dev, address, val, len);
+ piix_write_config(dev, address, val, len);
}
static void piix_reset(DeviceState *dev)
@@ -226,7 +226,7 @@ static int piix3_post_load(void *opaque, int version_id)
*/
piix3->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level_internal(piix3, pirq,
+ piix_set_irq_level_internal(piix3, pirq,
pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
}
return 0;
@@ -473,7 +473,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
- pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
+ pci_bus_irqs(pci_bus, piix_set_irq, piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
@@ -481,7 +481,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->config_write = piix3_write_config;
+ k->config_write = piix_write_config;
k->realize = piix3_realize;
}
--
2.39.2
- [PATCH v8 12/23] hw/isa/piix3: Drop the "3" from PIIX base class, (continued)
- [PATCH v8 12/23] hw/isa/piix3: Drop the "3" from PIIX base class, Bernhard Beschow, 2023/03/02
- [PATCH v8 10/23] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2023/03/02
- [PATCH v8 14/23] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Bernhard Beschow, 2023/03/02
- [PATCH v8 16/23] hw/isa/piix4: Create the "intr" property during init() already, Bernhard Beschow, 2023/03/02
- [PATCH v8 17/23] hw/isa/piix4: Rename reset control operations to match PIIX3, Bernhard Beschow, 2023/03/02
- [PATCH v8 13/23] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional, Bernhard Beschow, 2023/03/02
- [PATCH v8 15/23] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Bernhard Beschow, 2023/03/02
- [PATCH v8 19/23] hw/isa/piix: Harmonize names of reset control memory regions, Bernhard Beschow, 2023/03/02
- [PATCH v8 18/23] hw/isa/piix3: Merge hw/isa/piix4.c, Bernhard Beschow, 2023/03/02
- [PATCH v8 21/23] hw/isa/piix: Consolidate IRQ triggering, Bernhard Beschow, 2023/03/02
- [PATCH v8 20/23] hw/isa/piix: Rename functions to be shared for interrupt triggering,
Bernhard Beschow <=
- [PATCH v8 22/23] hw/isa/piix: Share PIIX3's base class with PIIX4, Bernhard Beschow, 2023/03/02
- [PATCH v8 23/23] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4, Bernhard Beschow, 2023/03/02