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[PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs
From: |
Bin Meng |
Subject: |
[PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs |
Date: |
Tue, 28 Feb 2023 21:45:33 +0800 |
From: Bin Meng <bmeng@tinylab.org>
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
(no changes since v1)
target/riscv/csr.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e70f5ba0..020c3f524f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
--
2.25.1
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, (continued)
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, Bin Meng, 2023/02/28
- [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only, Bin Meng, 2023/02/28
- [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/28
- [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env, Bin Meng, 2023/02/28
- [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Bin Meng, 2023/02/28
- [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Bin Meng, 2023/02/28
- [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs, Bin Meng, 2023/02/28
- [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR, Bin Meng, 2023/02/28
- [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/28
- [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs, Bin Meng, 2023/02/28
- [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs,
Bin Meng <=
- [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate(), Bin Meng, 2023/02/28
- [PATCH v2 18/18] target/riscv: Group all predicate() routines together, Bin Meng, 2023/02/28