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[PATCH v2 13/18] target/riscv: Allow debugger to access user timer and c
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From: |
Bin Meng |
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Subject: |
[PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs |
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Date: |
Tue, 28 Feb 2023 21:45:30 +0800 |
From: Bin Meng <bmeng@tinylab.org>
At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.
Fix it by adding a debugger check in their predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7284fd8a0d..10ae5df5e6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
skip_ext_pmu_check:
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
- [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check, (continued)
- [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check, Bin Meng, 2023/02/28
- [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability, Bin Meng, 2023/02/28
- [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Bin Meng, 2023/02/28
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, Bin Meng, 2023/02/28
- [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only, Bin Meng, 2023/02/28
- [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/28
- [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env, Bin Meng, 2023/02/28
- [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Bin Meng, 2023/02/28
- [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Bin Meng, 2023/02/28
- [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs,
Bin Meng <=
- [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR, Bin Meng, 2023/02/28
- [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/28
- [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs, Bin Meng, 2023/02/28
- [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs, Bin Meng, 2023/02/28
- [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate(), Bin Meng, 2023/02/28
- [PATCH v2 18/18] target/riscv: Group all predicate() routines together, Bin Meng, 2023/02/28