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[PATCH v1] target/loongarch: Implement Chip Configuraiton Version Regist
From: |
Song Gao |
Subject: |
[PATCH v1] target/loongarch: Implement Chip Configuraiton Version Register(0x0000) |
Date: |
Mon, 27 Feb 2023 15:10:46 +0800 |
According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x0000). The manual does not state that 0x0018 is
reserved for the vendor name and 0x0028 is reserved for the chip name.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 290ab4d526..d1c803c9d6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -545,6 +545,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr,
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
{
switch (addr) {
+ case VERSION_REG:
+ return 0x11ULL;
case FEATURE_REG:
return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
1ULL << IOCSRF_CSRIPI;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index e35cf65597..eabb66fe2f 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -27,9 +27,12 @@
#define IOCSRF_GMOD 9
#define IOCSRF_VM 11
+#define VERSION_REG 0x0
#define FEATURE_REG 0x8
#define VENDOR_REG 0x10
+#define VENDOR_RESERVED_REG 0x18
#define CPUNAME_REG 0x20
+#define CPUNAME_RESERVED_REG 0x28
#define MISC_FUNC_REG 0x420
#define IOCSRM_EXTIOI_EN 48
--
2.31.1
- [PATCH v1] target/loongarch: Implement Chip Configuraiton Version Register(0x0000),
Song Gao <=