Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw

[Richard Henderson]

On 2/22/23 22:23, gaosong wrote:
> Hi, Richard
>
> 在 2023/2/21 上午1:21, Richard Henderson 写道:
> > On 2/19/23 21:47, gaosong wrote:
> > > I have some questions:
> > > 1 Should we need implement  GVecGen*  for simple gvec instructiosn?
> > >      such as add, sub , or , xor..
> >
> > No, these are done generically.
> >
> > > 2 Should we need implement all fni8/fni4, fniv,  fno?
> >
> > You need not implement them all.  Generally you will only implement fni4 for 32-bit 
> > arithmetic operations, and only fni8 for logical operations; there is rarely a cause for 
> > both with the same operation.
> >
> > You can rely on the generic cutoff of 4 integer inline operations -- easy for your 
> > maximum vector length of 128-bits -- to avoid implementing fno.
> >
> > But in extreme, you can implement only fno.  You can choose this over directly calling a 
> > helper function, minimizing differences in the translator code paths and letting generic 
> > code build all of the pointers.
> Sorry for the late reply,  and Thanks for you answers.
>
> But I still need more help.
>
> How gvec singed or unsigned extensions of vector elements?

There are no generic sign-extending; that turns out to be widely variable across the 
different hosts and guest architectures.

If your architecture widens the even elements, you can implement extensions as a pair of 
shifts in the wider element size.  E.g. sign-extend is shl + sar.

> I found no gvec function that implements signed and unsigned extensions of 
> vector elements.
> However, the result of some instructions requires the elements to be signed or unsigned 
> extensions.

You may need to implement these operations with fni[48] or out of line in a 
helper.
It's hard to give advice without a specific example.


r~