Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw

[gaosong]

Hi, Richard

在 2022/12/25 上午1:48, Richard Henderson 写道:
> On 12/24/22 00:16, Song Gao wrote:
> > +TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b)
> > +TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h)
> > +TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w)
> > +TRANS(vaddwev_q_d, gen_vvv, gen_helper_vaddwev_q_d)
> > +TRANS(vaddwod_h_b, gen_vvv, gen_helper_vaddwod_h_b)
> > +TRANS(vaddwod_w_h, gen_vvv, gen_helper_vaddwod_w_h)
> > +TRANS(vaddwod_d_w, gen_vvv, gen_helper_vaddwod_d_w)
> > +TRANS(vaddwod_q_d, gen_vvv, gen_helper_vaddwod_q_d)
> > +TRANS(vsubwev_h_b, gen_vvv, gen_helper_vsubwev_h_b)
> > +TRANS(vsubwev_w_h, gen_vvv, gen_helper_vsubwev_w_h)
> > +TRANS(vsubwev_d_w, gen_vvv, gen_helper_vsubwev_d_w)
> > +TRANS(vsubwev_q_d, gen_vvv, gen_helper_vsubwev_q_d)
> > +TRANS(vsubwod_h_b, gen_vvv, gen_helper_vsubwod_h_b)
> > +TRANS(vsubwod_w_h, gen_vvv, gen_helper_vsubwod_w_h)
> > +TRANS(vsubwod_d_w, gen_vvv, gen_helper_vsubwod_d_w)
> > +TRANS(vsubwod_q_d, gen_vvv, gen_helper_vsubwod_q_d)
>
> These can be implemented with a combination of vector shift + vector add.
>
> > +TRANS(vaddwev_h_bu, gen_vvv, gen_helper_vaddwev_h_bu)
> > +TRANS(vaddwev_w_hu, gen_vvv, gen_helper_vaddwev_w_hu)
> > +TRANS(vaddwev_d_wu, gen_vvv, gen_helper_vaddwev_d_wu)
> > +TRANS(vaddwev_q_du, gen_vvv, gen_helper_vaddwev_q_du)
> > +TRANS(vaddwod_h_bu, gen_vvv, gen_helper_vaddwod_h_bu)
> > +TRANS(vaddwod_w_hu, gen_vvv, gen_helper_vaddwod_w_hu)
> > +TRANS(vaddwod_d_wu, gen_vvv, gen_helper_vaddwod_d_wu)
> > +TRANS(vaddwod_q_du, gen_vvv, gen_helper_vaddwod_q_du)
> > +TRANS(vsubwev_h_bu, gen_vvv, gen_helper_vsubwev_h_bu)
> > +TRANS(vsubwev_w_hu, gen_vvv, gen_helper_vsubwev_w_hu)
> > +TRANS(vsubwev_d_wu, gen_vvv, gen_helper_vsubwev_d_wu)
> > +TRANS(vsubwev_q_du, gen_vvv, gen_helper_vsubwev_q_du)
> > +TRANS(vsubwod_h_bu, gen_vvv, gen_helper_vsubwod_h_bu)
> > +TRANS(vsubwod_w_hu, gen_vvv, gen_helper_vsubwod_w_hu)
> > +TRANS(vsubwod_d_wu, gen_vvv, gen_helper_vsubwod_d_wu)
> > +TRANS(vsubwod_q_du, gen_vvv, gen_helper_vsubwod_q_du)
>
> These can be implemented with a combination of vector and + vector add.
>
> > +TRANS(vaddwev_h_bu_b, gen_vvv, gen_helper_vaddwev_h_bu_b)
> > +TRANS(vaddwev_w_hu_h, gen_vvv, gen_helper_vaddwev_w_hu_h)
> > +TRANS(vaddwev_d_wu_w, gen_vvv, gen_helper_vaddwev_d_wu_w)
> > +TRANS(vaddwev_q_du_d, gen_vvv, gen_helper_vaddwev_q_du_d)
> > +TRANS(vaddwod_h_bu_b, gen_vvv, gen_helper_vaddwod_h_bu_b)
> > +TRANS(vaddwod_w_hu_h, gen_vvv, gen_helper_vaddwod_w_hu_h)
> > +TRANS(vaddwod_d_wu_w, gen_vvv, gen_helper_vaddwod_d_wu_w)
> > +TRANS(vaddwod_q_du_d, gen_vvv, gen_helper_vaddwod_q_du_d)
>
> Likewise.
>
> For an example of how to bundle vector operations, see e.g. 
> gen_gvec_rax1 and subroutines in target/arm/translate-a64.c. There are 
> many others, but ask if you need more help.
I have some questions:
1 Should we need implement  GVecGen*  for simple gvec instructiosn?
    such as add, sub , or , xor..
2 Should we need implement all fni8/fni4, fniv,  fno?

Thanks
Song Gao