|
From: | pierre |
Subject: | Re: [PATCH v16 03/11] target/s390x/cpu topology: handle STSI(15) and build the SYSIB |
Date: | Thu, 23 Feb 2023 15:27:50 +0100 |
On 2023-02-23 14:30, Thomas Huth wrote:
On 22/02/2023 15.20, Pierre Morel wrote:On interception of STSI(15.1.x) the System Information Block (SYSIB) is built from the list of pre-ordered topology entries. Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> ---...diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index d654267a71..c899f4e04b 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -560,6 +560,25 @@ typedef struct SysIB_322 { } SysIB_322; QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); +#define S390_TOPOLOGY_MAG 6 +#define S390_TOPOLOGY_MAG6 0 +#define S390_TOPOLOGY_MAG5 1 +#define S390_TOPOLOGY_MAG4 2 +#define S390_TOPOLOGY_MAG3 3 +#define S390_TOPOLOGY_MAG2 4 +#define S390_TOPOLOGY_MAG1 5 +/* Configuration topology */ +typedef struct SysIB_151x { + uint8_t reserved0[2]; + uint16_t length; + uint8_t mag[S390_TOPOLOGY_MAG]; + uint8_t reserved1; + uint8_t mnest; + uint32_t reserved2; + char tle[]; +} QEMU_PACKED QEMU_ALIGNED(8) SysIB_151x; +QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16);I think one of the two is enough, either QEMU_PACKED or QEMU_BUILD_BUG_ON. Since QEMU_PACKED caused us some troubles in the past already, I'd prefer QEMU_BUILD_BUG_ON only here. Also, do we really need the QEMU_ALIGNED() here? ... I don't think so, and we also hardly use that anywhere else in the s390x code, so please drop that, too (unless there is a real reason for this?).
No, I think we do not really need this.
@@ -567,9 +586,62 @@ typedef union SysIB { SysIB_221 sysib_221; SysIB_222 sysib_222; SysIB_322 sysib_322; + SysIB_151x sysib_151x; } SysIB; QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); +/* + * CPU Topology List provided by STSI with fc=15 provides a list + * of two different Topology List Entries (TLE) types to specify + * the topology hierarchy. + * + * - Container Topology List Entry + * Defines a container to contain other Topology List Entries + * of any type, nested containers or CPU. + * - CPU Topology List Entry + * Specifies the CPUs position, type, entitlement and polarization + * of the CPUs contained in the last Container TLE. + * + * There can be theoretically up to five levels of containers, QEMU + * uses only three levels, the drawer's, book's and socket's level. + * + * A container of with a nesting level (NL) greater than 1 can only + * contain another container of nesting level NL-1. + * + * A container of nesting level 1 (socket), contains as many CPU TLE+ * as needed to describe the position and qualities of all CPUs inside+ * the container. + * The qualities of a CPU are polarization, entitlement and type. + *+ * The CPU TLE defines the position of the CPUs of identical qualities+ * using a 64bits mask which first bit has its offset defined by + * the CPU address orgin field of the CPU TLE like in: + * CPU address = origin * 64 + bit position within the mask + * + */ +/* Container type Topology List Entry */ +typedef struct SysIBTl_container { + uint8_t nl; + uint8_t reserved[6]; + uint8_t id; +} QEMU_PACKED QEMU_ALIGNED(8) SysIBTl_container;dito, please drop QEMU_PACKED and QEMU_ALIGNED() if possible.
OK
+QEMU_BUILD_BUG_ON(sizeof(SysIBTl_container) != 8); + +/* CPU type Topology List Entry */ +typedef struct SysIBTl_cpu { + uint8_t nl; + uint8_t reserved0[3]; +#define SYSIB_TLE_POLARITY_MASK 0x03 +#define SYSIB_TLE_DEDICATED 0x04 + uint8_t flags; + uint8_t type; + uint16_t origin; + uint64_t mask; +} QEMU_PACKED QEMU_ALIGNED(8) SysIBTl_cpu;dito
OK
Thomas
Thanks Pierre
[Prev in Thread] | Current Thread | [Next in Thread] |