"A cache-block zero instruction is permitted to access the specified cache
block whenever
a store instruction is permitted to access the corresponding physical addresses
and when
the PMAs indicate that cache-block zero instructions are a supported access
type. If access
to the cache block is not permitted, a cache-block zero instruction raises a
store page fault
or store guest-page fault exception if address translation does not permit
write access or
raises a store access fault exception otherwise. During address translation,
the instruction
also checks the accessed and dirty bits and may either raise an exception or
set the bits as
required."