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[PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c
From: |
Richard Henderson |
Subject: |
[PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c |
Date: |
Wed, 15 Feb 2023 17:08:53 -1000 |
With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise
an alignment exception when the load crosses a 16-byte boundary.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/multiarch/sigbus.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c
index 8134c5fd56..f47c7390e7 100644
--- a/tests/tcg/multiarch/sigbus.c
+++ b/tests/tcg/multiarch/sigbus.c
@@ -6,8 +6,13 @@
#include <endian.h>
-unsigned long long x = 0x8877665544332211ull;
-void * volatile p = (void *)&x + 1;
+char x[32] __attribute__((aligned(16))) = {
+ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
+ 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
+ 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20,
+};
+void * volatile p = (void *)&x + 15;
void sigbus(int sig, siginfo_t *info, void *uc)
{
@@ -60,9 +65,9 @@ int main()
* We might as well validate the unaligned load worked.
*/
if (BYTE_ORDER == LITTLE_ENDIAN) {
- assert(tmp == 0x55443322);
+ assert(tmp == 0x13121110);
} else {
- assert(tmp == 0x77665544);
+ assert(tmp == 0x10111213);
}
return EXIT_SUCCESS;
}
--
2.34.1
- Re: [PATCH v1 13/19] target/arm: Pass single_memop to gen_mte_checkN, (continued)
[PATCH v1 17/19] target/arm: Move mte check for store-exclusive, Richard Henderson, 2023/02/15
[PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c,
Richard Henderson <=
[PATCH v1 19/19] target/arm: Enable FEAT_LSE2 for -cpu max, Richard Henderson, 2023/02/15