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[PATCH v1 15/19] target/arm: Add SCTLR.nAA to TBFLAG_A64
From: |
Richard Henderson |
Subject: |
[PATCH v1 15/19] target/arm: Add SCTLR.nAA to TBFLAG_A64 |
Date: |
Wed, 15 Feb 2023 17:08:50 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 3 ++-
target/arm/translate.h | 2 ++
target/arm/helper.c | 6 ++++++
target/arm/translate-a64.c | 1 +
4 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2108caf753..b814c52469 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1243,7 +1243,7 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
#define SCTLR_CP15BEN (1U << 5) /* v7 onward */
#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
-#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
+#define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
#define SCTLR_ITD (1U << 7) /* v8 onward */
#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
@@ -3247,6 +3247,7 @@ FIELD(TBFLAG_A64, SVL, 24, 4)
/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
+FIELD(TBFLAG_A64, NAA, 30, 1)
/*
* Helpers for using the above.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 809479f9b7..46a60f8987 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -137,6 +137,8 @@ typedef struct DisasContext {
bool fgt_eret;
/* True if fine-grained trap on SVC is enabled */
bool fgt_svc;
+ /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
+ bool naa;
/*
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
* < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c62ed05c12..d1683155a1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12053,6 +12053,12 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState
*env, int el, int fp_el,
}
}
+ if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) {
+ if (sctlr & SCTLR_nAA) {
+ DP_TBFLAG_A64(flags, NAA, 1);
+ }
+ }
+
/* Compute the condition for using AccType_UNPRIV for LDTR et al. */
if (!(env->pstate & PSTATE_UAO)) {
switch (mmu_idx) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index caeb91efa5..56c9d63664 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14813,6 +14813,7 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
+ dc->naa = EX_TBFLAG_A64(tb_flags, NAA);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
--
2.34.1
- [PATCH v1 11/19] target/arm: Hoist finalize_memop out of do_fp_{ld, st}, (continued)
- [PATCH v1 11/19] target/arm: Hoist finalize_memop out of do_fp_{ld, st}, Richard Henderson, 2023/02/15
- [PATCH v1 12/19] target/arm: Pass memop to gen_mte_check1*, Richard Henderson, 2023/02/15
- [PATCH v1 14/19] target/arm: Check alignment in helper_mte_check, Richard Henderson, 2023/02/15
- [PATCH v1 13/19] target/arm: Pass single_memop to gen_mte_checkN, Richard Henderson, 2023/02/15
- [PATCH v1 15/19] target/arm: Add SCTLR.nAA to TBFLAG_A64,
Richard Henderson <=
- [PATCH v1 16/19] target/arm: Relax ordered/atomic alignment checks for LSE2, Richard Henderson, 2023/02/15
[PATCH v1 17/19] target/arm: Move mte check for store-exclusive, Richard Henderson, 2023/02/15
[PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c, Richard Henderson, 2023/02/15