[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved
From: |
Richard Henderson |
Subject: |
[PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved |
Date: |
Wed, 15 Feb 2023 16:57:35 -1000 |
While we do not include these in tcg_target_reg_alloc_order,
and therefore they ought never be allocated, it seems safer
to mark them reserved as well.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 5dcea7e198..21442c9339 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -4232,6 +4232,19 @@ static void tcg_target_init(TCGContext *s)
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+#ifdef _WIN64
+ /* These are call saved, and we don't save them, so don't use them. */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15);
+#endif
}
typedef struct {
--
2.34.1
- [PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc, (continued)
- [PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc, Richard Henderson, 2023/02/15
- [PATCH v2 17/30] tcg/aarch64: Detect have_lse, have_lse2 for linux, Richard Henderson, 2023/02/15
- [PATCH v2 19/30] accel/tcg: Add have_lse2 support in ldst_atomicity, Richard Henderson, 2023/02/15
- [PATCH v2 18/30] tcg/aarch64: Detect have_lse, have_lse2 for darwin, Richard Henderson, 2023/02/15
- [PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK, Richard Henderson, 2023/02/15
- [PATCH v2 22/30] tcg/i386: Introduce tcg_out_mov2, Richard Henderson, 2023/02/15
- [PATCH v2 21/30] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2023/02/15
- [PATCH v2 23/30] tcg/i386: Introduce tcg_out_testi, Richard Henderson, 2023/02/15
- [PATCH v2 24/30] tcg/i386: Use full load/store helpers in user-only mode, Richard Henderson, 2023/02/15
- [PATCH v2 25/30] tcg/i386: Replace is64 with type in qemu_ld/st routines, Richard Henderson, 2023/02/15
- [PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved,
Richard Henderson <=
- [PATCH v2 27/30] tcg/i386: Examine MemOp for atomicity and alignment, Richard Henderson, 2023/02/15
- [PATCH v2 28/30] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2023/02/15
- [PATCH v2 29/30] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool, Richard Henderson, 2023/02/15
- [PATCH v2 30/30] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2023/02/15