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[PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK
From: |
Richard Henderson |
Subject: |
[PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK |
Date: |
Wed, 15 Feb 2023 16:57:29 -1000 |
Reorg TCG_OPF_64BIT and TCG_OPF_VECTOR into a two-bit field so
that we can add TCG_OPF_128BIT without requiring another bit.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 22 ++++++++++++----------
tcg/optimize.c | 15 ++++++++++++---
tcg/tcg.c | 4 ++--
tcg/aarch64/tcg-target.c.inc | 8 +++++---
tcg/tci/tcg-target.c.inc | 3 ++-
5 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 59854f95b1..23369541fe 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -987,24 +987,26 @@ typedef struct TCGArgConstraint {
/* Bits for TCGOpDef->flags, 8 bits available, all used. */
enum {
+ /* Two bits describing the output type. */
+ TCG_OPF_TYPE_MASK = 0x03,
+ TCG_OPF_32BIT = 0x00,
+ TCG_OPF_64BIT = 0x01,
+ TCG_OPF_VECTOR = 0x02,
+ TCG_OPF_128BIT = 0x03,
/* Instruction exits the translation block. */
- TCG_OPF_BB_EXIT = 0x01,
+ TCG_OPF_BB_EXIT = 0x04,
/* Instruction defines the end of a basic block. */
- TCG_OPF_BB_END = 0x02,
+ TCG_OPF_BB_END = 0x08,
/* Instruction clobbers call registers and potentially update globals. */
- TCG_OPF_CALL_CLOBBER = 0x04,
+ TCG_OPF_CALL_CLOBBER = 0x10,
/* Instruction has side effects: it cannot be removed if its outputs
are not used, and might trigger exceptions. */
- TCG_OPF_SIDE_EFFECTS = 0x08,
- /* Instruction operands are 64-bits (otherwise 32-bits). */
- TCG_OPF_64BIT = 0x10,
+ TCG_OPF_SIDE_EFFECTS = 0x20,
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
- TCG_OPF_NOT_PRESENT = 0x20,
- /* Instruction operands are vectors. */
- TCG_OPF_VECTOR = 0x40,
+ TCG_OPF_NOT_PRESENT = 0x40,
/* Instruction is a conditional branch. */
- TCG_OPF_COND_BRANCH = 0x80
+ TCG_OPF_COND_BRANCH = 0x80,
};
typedef struct TCGOpDef {
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 763bca9ea6..5c0bd6b6e6 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2053,12 +2053,21 @@ void tcg_optimize(TCGContext *s)
copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
/* Pre-compute the type of the operation. */
- if (def->flags & TCG_OPF_VECTOR) {
+ switch (def->flags & TCG_OPF_TYPE_MASK) {
+ case TCG_OPF_VECTOR:
ctx.type = TCG_TYPE_V64 + TCGOP_VECL(op);
- } else if (def->flags & TCG_OPF_64BIT) {
+ break;
+ case TCG_OPF_128BIT:
+ ctx.type = TCG_TYPE_I128;
+ break;
+ case TCG_OPF_64BIT:
ctx.type = TCG_TYPE_I64;
- } else {
+ break;
+ case TCG_OPF_32BIT:
ctx.type = TCG_TYPE_I32;
+ break;
+ default:
+ qemu_build_not_reached();
}
/* Assume all bits affected, no bits known zero, no sign reps. */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a4a3da6804..07522d50ee 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2118,7 +2118,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool
have_prefs)
nb_iargs = def->nb_iargs;
nb_cargs = def->nb_cargs;
- if (def->flags & TCG_OPF_VECTOR) {
+ if ((def->flags & TCG_OPF_TYPE_MASK) == TCG_OPF_VECTOR) {
col += ne_fprintf(f, "v%d,e%d,", 64 << TCGOP_VECL(op),
8 << TCGOP_VECE(op));
}
@@ -4375,7 +4375,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
}
/* emit instruction */
- if (def->flags & TCG_OPF_VECTOR) {
+ if ((def->flags & TCG_OPF_TYPE_MASK) == TCG_OPF_VECTOR) {
tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
new_args, const_args);
} else {
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 1a295791b4..6e40a453e6 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1922,9 +1922,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
- /* 99% of the time, we can signal the use of extension registers
- by looking to see if the opcode handles 64-bit data. */
- TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
+ /*
+ * 99% of the time, we can signal the use of extension registers
+ * by looking to see if the opcode handles 32-bit data or not.
+ */
+ TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_TYPE_MASK) !=
TCG_OPF_32BIT;
/* Hoist the loads of the most common arguments. */
TCGArg a0 = args[0];
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c1d34d7bd1..570b8c160e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -697,7 +697,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
{
TCGArg pos = args[2], len = args[3];
- TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+ TCGArg max = ((tcg_op_defs[opc].flags & TCG_OPF_TYPE_MASK)
+ == TCG_OPF_32BIT ? 32 : 64);
tcg_debug_assert(pos < max);
tcg_debug_assert(pos + len <= max);
--
2.34.1
- [PATCH v2 10/30] tcg: Unify helper_{be,le}_{ld,st}*, (continued)
- [PATCH v2 10/30] tcg: Unify helper_{be,le}_{ld,st}*, Richard Henderson, 2023/02/15
- [PATCH v2 13/30] meson: Detect atomic128 support with optimization, Richard Henderson, 2023/02/15
- [PATCH v2 11/30] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2023/02/15
- [PATCH v2 12/30] tcg: Add 128-bit guest memory primitives, Richard Henderson, 2023/02/15
- [PATCH v2 16/30] accel/tcg: Add aarch64 specific support in ldst_atomicity, Richard Henderson, 2023/02/15
- [PATCH v2 14/30] tcg/i386: Add have_atomic16, Richard Henderson, 2023/02/15
- [PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc, Richard Henderson, 2023/02/15
- [PATCH v2 17/30] tcg/aarch64: Detect have_lse, have_lse2 for linux, Richard Henderson, 2023/02/15
- [PATCH v2 19/30] accel/tcg: Add have_lse2 support in ldst_atomicity, Richard Henderson, 2023/02/15
- [PATCH v2 18/30] tcg/aarch64: Detect have_lse, have_lse2 for darwin, Richard Henderson, 2023/02/15
- [PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK,
Richard Henderson <=
- [PATCH v2 22/30] tcg/i386: Introduce tcg_out_mov2, Richard Henderson, 2023/02/15
- [PATCH v2 21/30] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2023/02/15
- [PATCH v2 23/30] tcg/i386: Introduce tcg_out_testi, Richard Henderson, 2023/02/15
- [PATCH v2 24/30] tcg/i386: Use full load/store helpers in user-only mode, Richard Henderson, 2023/02/15
- [PATCH v2 25/30] tcg/i386: Replace is64 with type in qemu_ld/st routines, Richard Henderson, 2023/02/15
- [PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved, Richard Henderson, 2023/02/15
- [PATCH v2 27/30] tcg/i386: Examine MemOp for atomicity and alignment, Richard Henderson, 2023/02/15
- [PATCH v2 28/30] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2023/02/15
- [PATCH v2 29/30] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool, Richard Henderson, 2023/02/15
- [PATCH v2 30/30] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2023/02/15