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[PATCH v2 04/14] target/riscv: Add cfg properties for Zv* extensions
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From: |
Weiwei Li |
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Subject: |
[PATCH v2 04/14] target/riscv: Add cfg properties for Zv* extensions |
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Date: |
Wed, 15 Feb 2023 10:05:29 +0800 |
Add properties for Zve64d,Zvfh,Zvfhmin extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..54c6875617 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,7 +462,10 @@ struct RISCVCPUConfig {
bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
+ bool ext_zve64d;
bool ext_zmmul;
+ bool ext_zvfh;
+ bool ext_zvfhmin;
bool ext_smaia;
bool ext_ssaia;
bool ext_sscofpmf;
--
2.25.1
- [PATCH v2 00/14] target/riscv: Some updates to float point related extensions, Weiwei Li, 2023/02/14
- [PATCH v2 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Weiwei Li, 2023/02/14
- [PATCH v2 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Weiwei Li, 2023/02/14
- [PATCH v2 04/14] target/riscv: Add cfg properties for Zv* extensions,
Weiwei Li <=
- [PATCH v2 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
- [PATCH v2 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Weiwei Li, 2023/02/14
- [PATCH v2 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Weiwei Li, 2023/02/14
- [PATCH v2 07/14] target/riscv: Indent fixes in cpu.c, Weiwei Li, 2023/02/14
- [PATCH v2 14/14] target/riscv: Expose properties for Zv* extensions, Weiwei Li, 2023/02/14
- [PATCH v2 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
- [PATCH v2 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
- [PATCH v2 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Weiwei Li, 2023/02/14
- [PATCH v2 12/14] target/riscv: Fix check for vector load/store instructions when EEW=64, Weiwei Li, 2023/02/14
- [PATCH v2 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14