Re: [PATCH 05/14] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml

[Fabiano Rosas]

Richard Henderson <richard.henderson@linaro.org> writes:

> Rather than increment base_reg and num, compute num
> from the change to base_reg at the end.  Clean up some
> nearby comments.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/gdbstub64.c | 26 ++++++++++++++++----------
>  1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
> index 811833d8de..8d174ff6e0 100644
> --- a/target/arm/gdbstub64.c
> +++ b/target/arm/gdbstub64.c
> @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int 
> reg_width)
>      g_string_append(s, "</union>");
>  }
>  
> -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
> +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
>  {
>      ARMCPU *cpu = ARM_CPU(cs);
>      GString *s = g_string_new(NULL);
>      DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
> -    int i, reg_width = (cpu->sve_max_vq * 128);
> -    info->num = 0;
> +    int reg_width = cpu->sve_max_vq * 128;
> +    int base_reg = orig_base_reg;
> +    int i;
> +
>      g_string_printf(s, "<?xml version=\"1.0\"?>");
>      g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
>      g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
>  
> +    /* Create the vector union type. */
>      output_vector_union_type(s, reg_width);
>  
> -    /* Finally the sve prefix type */
> +    /* Create the predicate vector type. */
>      g_string_append_printf(s,
>                             "<vector id=\"svep\" type=\"uint8\" 
> count=\"%d\"/>",
>                             reg_width / 8);
>  
> -    /* Then define each register in parts for each vq */
> +    /* Define the vector registers. */
>      for (i = 0; i < 32; i++) {
>          g_string_append_printf(s,
>                                 "<reg name=\"z%d\" bitsize=\"%d\""
>                                 " regnum=\"%d\" type=\"svev\"/>",
>                                 i, reg_width, base_reg++);
> -        info->num++;
>      }
> +
>      /* fpscr & status registers */
>      g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
>                             " regnum=\"%d\" group=\"float\""
> @@ -310,8 +313,8 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
>      g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
>                             " regnum=\"%d\" group=\"float\""
>                             " type=\"int\"/>", base_reg++);
> -    info->num += 2;
>  
> +    /* Define the predicate registers. */
>      for (i = 0; i < 16; i++) {

There's a info->num++; at the end of this loop.

>          g_string_append_printf(s,
>                                 "<reg name=\"p%d\" bitsize=\"%d\""
> @@ -324,13 +327,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int 
> base_reg)
>                             " regnum=\"%d\" group=\"vector\""
>                             " type=\"svep\"/>",
>                             cpu->sve_max_vq * 16, base_reg++);
> +
> +    /* Define the vector length pseudo-register. */
>      g_string_append_printf(s,
>                             "<reg name=\"vg\" bitsize=\"64\""
>                             " regnum=\"%d\" type=\"int\"/>",
>                             base_reg++);
> -    info->num += 2;
> -    g_string_append_printf(s, "</feature>");
> -    info->desc = g_string_free(s, false);
>  
> +    g_string_append_printf(s, "</feature>");
> +
> +    info->desc = g_string_free(s, false);
> +    info->num = base_reg - orig_base_reg;
>      return info->num;
>  }