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[PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR
From: |
Bastian Koppelmann |
Subject: |
[PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR |
Date: |
Wed, 8 Feb 2023 10:14:17 +0100 |
if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the
right by 32 which is undefined behaviour. In this case the TriCore would
do nothing an just return the higher register cpu_reg_d[r1]. We fixed
that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower
register.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-8-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3b4ec530b1..8bf78b46d0 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8245,10 +8245,19 @@ static void decode_rrrr_extract_insert(DisasContext
*ctx)
if (r1 == r2) {
tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
+ TCGv msw = tcg_temp_new();
+ TCGv zero = tcg_constant_tl(0);
tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
- tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
- tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
- tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
+ tcg_gen_subfi_tl(msw, 32, tmp_pos);
+ tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
+ /*
+ * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
+ * behaviour. So check that case here and set the low bits to zero
+ * which effectivly returns cpu_gpr_d[r1]
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
+ tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
+ tcg_temp_free(msw);
}
break;
case OPC2_32_RRRR_EXTR:
--
2.39.1
- [PULL 00/12] tricore queue, Bastian Koppelmann, 2023/02/08
- [PULL 01/12] target/tricore: Fix OPC2_32_RCRW_IMASK translation, Bastian Koppelmann, 2023/02/08
- [PULL 02/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK, Bastian Koppelmann, 2023/02/08
- [PULL 04/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT, Bastian Koppelmann, 2023/02/08
- [PULL 03/12] target/tricore: Fix OPC2_32_RCRW_INSERT translation, Bastian Koppelmann, 2023/02/08
- [PULL 05/12] target/tricore: Fix RRPW_DEXTR, Bastian Koppelmann, 2023/02/08
- [PULL 06/12] tests/tcg/tricore: Add tests for RRPW_DEXTR, Bastian Koppelmann, 2023/02/08
- [PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR,
Bastian Koppelmann <=
- [PULL 08/12] tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests, Bastian Koppelmann, 2023/02/08
- [PULL 10/12] tests/tcg/tricore: Add LD.BU tests, Bastian Koppelmann, 2023/02/08
- [PULL 09/12] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC, Bastian Koppelmann, 2023/02/08
- [PULL 11/12] target/tricore: Fix OPC1_16_SRO_LD_H translation, Bastian Koppelmann, 2023/02/08
- [PULL 12/12] tests/tcg/tricore: Add test for ld.h, Bastian Koppelmann, 2023/02/08
- Re: [PULL 00/12] tricore queue, Peter Maydell, 2023/02/09