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[PULL 29/32] target/riscv: fix for virtual instr exception
From: |
Alistair Francis |
Subject: |
[PULL 29/32] target/riscv: fix for virtual instr exception |
Date: |
Tue, 7 Feb 2023 17:09:40 +1000 |
From: Deepak Gupta <debug@rivosinc.com>
commit fb3f3730e4 added mechanism to generate virtual instruction
exception during instruction decode when virt is enabled.
However in some situations, illegal instruction exception can be raised
due to state of CPU. One such situation is implementing branch tracking.
[1] An indirect branch if doesn't land on a landing pad instruction, then
cpu must raise an illegal instruction exception.
Implementation would raise such expcetion due to missing landing pad inst
and not due to decode. Thus DisasContext must have `virt_inst_excp`
initialized to false during DisasContxt initialization for TB.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230127191758.755844-1-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 182649dcb6..772f9d7973 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1213,6 +1213,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
+ ctx->virt_inst_excp = false;
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
--
2.39.1
- [PULL 20/32] RISC-V: Adding XTheadCondMov ISA extension, (continued)
- [PULL 20/32] RISC-V: Adding XTheadCondMov ISA extension, Alistair Francis, 2023/02/07
- [PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions, Alistair Francis, 2023/02/07
- [PULL 22/32] RISC-V: Adding T-Head MemPair extension, Alistair Francis, 2023/02/07
- [PULL 23/32] RISC-V: Adding T-Head MemIdx extension, Alistair Francis, 2023/02/07
- [PULL 24/32] RISC-V: Adding T-Head FMemIdx extension, Alistair Francis, 2023/02/07
- [PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11, Alistair Francis, 2023/02/07
- [PULL 26/32] RISC-V: Add initial support for T-Head C906, Alistair Francis, 2023/02/07
- [PULL 27/32] RISC-V: Adding XTheadFmv ISA extension, Alistair Francis, 2023/02/07
- [PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support, Alistair Francis, 2023/02/07
- [PULL 31/32] target/riscv: fix SBI getchar handler for KVM, Alistair Francis, 2023/02/07
- [PULL 29/32] target/riscv: fix for virtual instr exception,
Alistair Francis <=
- [PULL 32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint(), Alistair Francis, 2023/02/07
- [PULL 30/32] target/riscv: fix ctzw behavior, Alistair Francis, 2023/02/07
- Re: [PULL 00/32] riscv-to-apply queue, Peter Maydell, 2023/02/07