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[PATCH v2 04/11] target/arm: Constify ID_PFR1 on user emulation
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 04/11] target/arm: Constify ID_PFR1 on user emulation |
Date: |
Mon, 6 Feb 2023 23:34:55 +0100 |
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/helper.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c62ed05c12..22670c20c0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu)
}
}
+#ifndef CONFIG_USER_ONLY
/*
* We don't know until after realize whether there's a GICv3
* attached, and that is what registers the gicv3 sysregs.
@@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const
ARMCPRegInfo *ri)
return pfr1;
}
-#ifndef CONFIG_USER_ONLY
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
@@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_NO_RAW,
.accessfn = access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+ .type = ARM_CP_CONST,
+ .resetvalue = cpu->isar.id_pfr1,
+#else
+ .type = ARM_CP_NO_RAW,
+ .accessfn = access_aa32_tid3,
.readfn = id_pfr1_read,
- .writefn = arm_cp_write_ignore },
+ .writefn = arm_cp_write_ignore
+#endif
+ },
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
--
2.38.1
- [PATCH v2 00/11] target/arm: Housekeeping around NVIC, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 03/11] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 04/11] target/arm: Constify ID_PFR1 on user emulation,
Philippe Mathieu-Daudé <=
- [PATCH v2 05/11] target/arm: Convert CPUARMState::eabi to boolean, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 01/11] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 02/11] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 06/11] target/arm: Avoid resetting CPUARMState::eabi field, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 07/11] target/arm: Restrict CPUARMState::gicv3state to sysemu, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 08/11] target/arm: Restrict CPUARMState::arm_boot_info to sysemu, Philippe Mathieu-Daudé, 2023/02/06
- [PATCH v2 09/11] target/arm: Restrict CPUARMState::nvic to sysemu, Philippe Mathieu-Daudé, 2023/02/06