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Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi]
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From: |
Philipp Tomsich |
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Subject: |
Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support |
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Date: |
Thu, 2 Feb 2023 19:07:09 +0100 |
On Thu, 2 Feb 2023 at 18:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 2/2/23 04:30, Philipp Tomsich wrote:
> > On the second pass over these patches, here's how we can use gvec
> > support for both vror and vrol:
> >
> > /* Synthesize a rotate-right from a negate(shift-amount) + rotate-left */
> > static void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
> > TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
> > {
> > TCGv_i32 tmp = tcg_temp_new_i32();
> > tcg_gen_neg_i32(tmp, shift);
> > tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz);
>
> We can add rotls generically.
> I hadn't done this so far because there were no users.
I read this such that your preference is to have a generic gvec rotrs?
If this is correct, I can drop a patch to that effect…
Philipp.
- [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support, (continued)
- [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 23/39] target/riscv: expose zvkns cpu property, Lawrence Hunter, 2023/02/02
- [PATCH 04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- [PATCH 11/39] target/riscv: add zvkns cpu property, Lawrence Hunter, 2023/02/02
- [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/02/02
- Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Philipp Tomsich, 2023/02/02
- Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Philipp Tomsich, 2023/02/02
- Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Richard Henderson, 2023/02/02
- Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support,
Philipp Tomsich <=
- Re: [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Richard Henderson, 2023/02/02
[PATCH 28/39] target/riscv: add zvksh cpu property, Lawrence Hunter, 2023/02/02
[PATCH 21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 16/39] target/riscv: Add vaesdm.vv decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 20/39] target/riscv: Add vaesem.vs decoding, translation and execution support, Lawrence Hunter, 2023/02/02
[PATCH 03/39] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/02/02