Re: [PATCH] target/mips: Properly set C0_CMGCRBase after CPU reset

[Jiaxun Yang]

> 2022年11月14日 16:25，Jiaxun Yang <jiaxun.yang@flygoat.com> 写道：
> 
> Value of C0_CMGCRBase will be reseted to default when cpu reset
> happens. In some cases software may move GCR base and then initiate
> a CPU reset, this will leave C0_CMGCRBase of reseted core incorrect.
> 
> Implement a callback in CMGCR device to allow C0_CMGCRBase and other
> global states to be overriden after CPU reset.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> This fixes SMP boot for Boston board.
> I'm not sure if it's the best palce to make such a callback,
> but we can add more global states such as BEV here in future.

Ping :-)

Any comments?

> ---
> hw/mips/cps.c        | 3 ++-
> hw/misc/mips_cmgcr.c | 5 +++++
> target/mips/cpu.c    | 4 +++-
> target/mips/cpu.h    | 4 ++++
> 4 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/mips/cps.c b/hw/mips/cps.c
> index 2b436700ce..29b10ff8d0 100644
> --- a/hw/mips/cps.c
> +++ b/hw/mips/cps.c
> @@ -98,6 +98,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
>         cpu_mips_clock_init(cpu);
> 
>         env = &cpu->env;
> +        env->gcr = &s->gcr;
>         if (cpu_mips_itu_supported(env)) {
>             itu_present = true;
>             /* Attach ITC Tag to the VP */
> @@ -158,7 +159,7 @@ static void mips_cps_realize(DeviceState *dev, Error 
> **errp)
>                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 
> 0));
> 
>     /* Global Configuration Registers */
> -    gcr_base = env->CP0_CMGCRBase << 4;
> +    gcr_base = GCR_BASE_ADDR;
> 
>     object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
>     object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
> diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
> index 3c8b37f700..f2108b7d32 100644
> --- a/hw/misc/mips_cmgcr.c
> +++ b/hw/misc/mips_cmgcr.c
> @@ -19,6 +19,11 @@
> #include "hw/qdev-properties.h"
> #include "hw/intc/mips_gic.h"
> 
> +void gcr_cpu_reset(struct MIPSGCRState *s, CPUMIPSState *env)
> +{
> +    env->CP0_CMGCRBase = s->gcr_base >> 4;
> +}
> +
> static inline bool is_cpc_connected(MIPSGCRState *s)
> {
>     return s->cpc_mr != NULL;
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index e997c1b9cb..d0a76b95f7 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -297,7 +297,9 @@ static void mips_cpu_reset(DeviceState *dev)
>         env->CP0_EBase |= (int32_t)0x80000000;
>     }
>     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
> -        env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
> +        if (env->gcr) {
> +            gcr_cpu_reset(env->gcr, env);
> +        }
>     }
>     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
>             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 0a085643a3..c345e6b1c7 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1154,6 +1154,7 @@ typedef struct CPUArchState {
>     CPUMIPSTLBContext *tlb;
>     void *irq[8];
>     struct MIPSITUState *itu;
> +    struct MIPSGCRState *gcr;
>     MemoryRegion *itc_tag; /* ITC Configuration Tags */
> #endif
> 
> @@ -1310,6 +1311,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int 
> level);
> /* mips_itu.c */
> void itc_reconfigure(struct MIPSITUState *tag);
> 
> +/* mips_cmgcr.c */
> +void gcr_cpu_reset(struct MIPSGCRState *s, CPUMIPSState *env);
> +
> #endif /* !CONFIG_USER_ONLY */
> 
> /* helper.c */
> -- 
> 2.37.4
>