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[PATCH for-8.0 01/29] include/qemu/cpuid: Introduce xgetbv_low
From: |
Richard Henderson |
Subject: |
[PATCH for-8.0 01/29] include/qemu/cpuid: Introduce xgetbv_low |
Date: |
Fri, 18 Nov 2022 01:47:26 -0800 |
Replace the two uses of asm to expand xgetbv with an inline function.
Since one of the two has been using the mnemonic, assume that the
comment about "older versions of the assember" is obsolete, as even
that is 4 years old.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/cpuid.h | 7 +++++++
util/bufferiszero.c | 3 +--
tcg/i386/tcg-target.c.inc | 11 ++++-------
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 7adb12d320..1451e8ef2f 100644
--- a/include/qemu/cpuid.h
+++ b/include/qemu/cpuid.h
@@ -71,4 +71,11 @@
#define bit_LZCNT (1 << 5)
#endif
+static inline unsigned xgetbv_low(unsigned c)
+{
+ unsigned a, d;
+ asm("xgetbv" : "=a"(a), "=d"(d) : "c"(c));
+ return a;
+}
+
#endif /* QEMU_CPUID_H */
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index ec3cd4ca15..b0660d484d 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -287,8 +287,7 @@ static void __attribute__((constructor))
init_cpuid_cache(void)
/* We must check that AVX is not just available, but usable. */
if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >= 7) {
- int bv;
- __asm("xgetbv" : "=a"(bv), "=d"(d) : "c"(0));
+ unsigned bv = xgetbv_low(0);
__cpuid_count(7, 0, a, b, c, d);
if ((bv & 0x6) == 0x6 && (b & bit_AVX2)) {
cache |= CACHE_AVX2;
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index c96b5a6f43..1361960156 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -4148,12 +4148,9 @@ static void tcg_target_init(TCGContext *s)
/* There are a number of things we must check before we can be
sure of not hitting invalid opcode. */
if (c & bit_OSXSAVE) {
- unsigned xcrl, xcrh;
- /* The xgetbv instruction is not available to older versions of
- * the assembler, so we encode the instruction manually.
- */
- asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0));
- if ((xcrl & 6) == 6) {
+ unsigned bv = xgetbv_low(0);
+
+ if ((bv & 6) == 6) {
have_avx1 = (c & bit_AVX) != 0;
have_avx2 = (b7 & bit_AVX2) != 0;
@@ -4164,7 +4161,7 @@ static void tcg_target_init(TCGContext *s)
* check that OPMASK and all extended ZMM state are enabled
* even if we're not using them -- the insns will fault.
*/
- if ((xcrl & 0xe0) == 0xe0
+ if ((bv & 0xe0) == 0xe0
&& (b7 & bit_AVX512F)
&& (b7 & bit_AVX512VL)) {
have_avx512vl = true;
--
2.34.1
- [PATCH for-8.0 00/29] tcg: Improve atomicity support, Richard Henderson, 2022/11/18
- [PATCH for-8.0 02/29] include/exec/memop: Add bits describing atomicity, Richard Henderson, 2022/11/18
- [PATCH for-8.0 03/29] accel/tcg: Add cpu_in_serial_context, Richard Henderson, 2022/11/18
- [PATCH for-8.0 04/29] accel/tcg: Introduce tlb_read_idx, Richard Henderson, 2022/11/18
- [PATCH for-8.0 05/29] accel/tcg: Reorg system mode load helpers, Richard Henderson, 2022/11/18
- [PATCH for-8.0 01/29] include/qemu/cpuid: Introduce xgetbv_low,
Richard Henderson <=
- [PATCH for-8.0 06/29] accel/tcg: Reorg system mode store helpers, Richard Henderson, 2022/11/18
- [PATCH for-8.0 07/29] accel/tcg: Honor atomicity of loads, Richard Henderson, 2022/11/18
- [PATCH for-8.0 09/29] tcg/tci: Use cpu_{ld,st}_mmu, Richard Henderson, 2022/11/18
- [PATCH for-8.0 08/29] accel/tcg: Honor atomicity of stores, Richard Henderson, 2022/11/18
- [PATCH for-8.0 11/29] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2022/11/18
- [PATCH for-8.0 10/29] tcg: Unify helper_{be,le}_{ld,st}*, Richard Henderson, 2022/11/18