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[PULL 04/14] target/mips: Disable DSP ASE for Octeon68XX
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 04/14] target/mips: Disable DSP ASE for Octeon68XX |
Date: |
Tue, 8 Nov 2022 00:58:12 +0100 |
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
I don't have access to Octeon68XX hardware but according
to my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <20221031132531.18122-4-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu-defs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 7f53c94ec8..480e60aeec 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -934,7 +934,7 @@ const mips_def_t mips_defs[] =
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
(0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
(3U << CP0C4_MMUSizeExt),
@@ -946,7 +946,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 49,
- .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+ .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
.mmu_type = MMU_TYPE_R4000,
},
--
2.38.1
- [PULL 00/14] MIPS patches for 2022-11-08, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 02/14] target/mips: Cast offset field of Octeon BBIT to int16_t, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 01/14] target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 03/14] target/mips: Enable LBX/LWX/* instructions for Octeon, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 04/14] target/mips: Disable DSP ASE for Octeon68XX,
Philippe Mathieu-Daudé <=
- [PULL 05/14] target/mips: Don't check COP1X for 64 bit FP mode, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 06/14] disas/nanomips: Fix invalid PRId64 format calling img_format(), Philippe Mathieu-Daudé, 2022/11/07
- [PULL 07/14] disas/nanomips: Fix invalid PRIx64 format calling img_format(), Philippe Mathieu-Daudé, 2022/11/07
- [PULL 08/14] disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 09/14] disas/nanomips: Remove headers already included by "qemu/osdep.h", Philippe Mathieu-Daudé, 2022/11/07
- [PULL 10/14] disas/nanomips: Move setjmp into nanomips_dis, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 11/14] disas/nanomips: Merge insn{1,2,3} into words[3], Philippe Mathieu-Daudé, 2022/11/07
- [PULL 12/14] disas/nanomips: Split out read_u16, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 13/14] disas/nanomips: Tidy read for 48-bit opcodes, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 14/14] MAINTAINERS: Inherit from nanoMIPS, Philippe Mathieu-Daudé, 2022/11/07