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[PULL 03/14] target/mips: Enable LBX/LWX/* instructions for Octeon
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 03/14] target/mips: Enable LBX/LWX/* instructions for Octeon |
Date: |
Tue, 8 Nov 2022 00:58:11 +0100 |
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 2f2d707a12..4c4bd0823d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -12173,12 +12173,16 @@ enum {
#include "nanomips_translate.c.inc"
/* MIPSDSP functions. */
-static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
- int rd, int base, int offset)
+
+/* Indexed load is not for DSP only */
+static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
+ int rd, int base, int offset)
{
TCGv t0;
- check_dsp(ctx);
+ if (!(ctx->insn_flags & INSN_OCTEON)) {
+ check_dsp(ctx);
+ }
t0 = tcg_temp_new();
if (base == 0) {
@@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_LBUX:
case OPC_LHX:
case OPC_LWX:
- gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
+ gen_mips_lx(ctx, op2, rd, rs, rt);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
--
2.38.1
- [PULL 00/14] MIPS patches for 2022-11-08, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 02/14] target/mips: Cast offset field of Octeon BBIT to int16_t, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 01/14] target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 03/14] target/mips: Enable LBX/LWX/* instructions for Octeon,
Philippe Mathieu-Daudé <=
- [PULL 04/14] target/mips: Disable DSP ASE for Octeon68XX, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 05/14] target/mips: Don't check COP1X for 64 bit FP mode, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 06/14] disas/nanomips: Fix invalid PRId64 format calling img_format(), Philippe Mathieu-Daudé, 2022/11/07
- [PULL 07/14] disas/nanomips: Fix invalid PRIx64 format calling img_format(), Philippe Mathieu-Daudé, 2022/11/07
- [PULL 08/14] disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 09/14] disas/nanomips: Remove headers already included by "qemu/osdep.h", Philippe Mathieu-Daudé, 2022/11/07
- [PULL 10/14] disas/nanomips: Move setjmp into nanomips_dis, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 11/14] disas/nanomips: Merge insn{1,2,3} into words[3], Philippe Mathieu-Daudé, 2022/11/07
- [PULL 12/14] disas/nanomips: Split out read_u16, Philippe Mathieu-Daudé, 2022/11/07
- [PULL 13/14] disas/nanomips: Tidy read for 48-bit opcodes, Philippe Mathieu-Daudé, 2022/11/07