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[PULL v3 27/81] hw/mem/cxl-type3: Add MSIX support
From: |
Michael S. Tsirkin |
Subject: |
[PULL v3 27/81] hw/mem/cxl-type3: Add MSIX support |
Date: |
Sat, 5 Nov 2022 13:16:47 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This will be used by several upcoming patch sets so break it out
such that it doesn't matter which one lands first.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/mem/cxl_type3.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index a71bf1afeb..568c9d62f5 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -13,6 +13,7 @@
#include "qemu/rcu.h"
#include "sysemu/hostmem.h"
#include "hw/cxl/cxl.h"
+#include "hw/pci/msix.h"
/*
* Null value of all Fs suggested by IEEE RA guidelines for use of
@@ -146,6 +147,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
ComponentRegisters *regs = &cxl_cstate->crb;
MemoryRegion *mr = ®s->component_registers;
uint8_t *pci_conf = pci_dev->config;
+ unsigned short msix_num = 1;
+ int i;
if (!cxl_setup_memory(ct3d, errp)) {
return;
@@ -180,6 +183,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64,
&ct3d->cxl_dstate.device_registers);
+
+ /* MSI(-X) Initailization */
+ msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
+ for (i = 0; i < msix_num; i++) {
+ msix_vector_use(pci_dev, i);
+ }
}
static void ct3_exit(PCIDevice *pci_dev)
--
MST
- [PULL v3 18/81] bios-tables-test: teach test to use smbios 3.0 tables, (continued)
- [PULL v3 18/81] bios-tables-test: teach test to use smbios 3.0 tables, Michael S. Tsirkin, 2022/11/05
- [PULL v3 21/81] tests/acpi: update tables for new core count test, Michael S. Tsirkin, 2022/11/05
- [PULL v3 23/81] acpi: fadt: support revision 6.0 of the ACPI specification, Michael S. Tsirkin, 2022/11/05
- [PULL v3 29/81] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange, Michael S. Tsirkin, 2022/11/05
- [PULL v3 22/81] tests/acpi: virt: allow acpi MADT and FADT changes, Michael S. Tsirkin, 2022/11/05
- [PULL v3 38/81] vhost: expose vhost_virtqueue_start(), Michael S. Tsirkin, 2022/11/05
- [PULL v3 55/81] acpi: enumerate SMB bridge automatically along with other PCI devices, Michael S. Tsirkin, 2022/11/05
- [PULL v3 58/81] acpi: pc/35: sanitize _GPE declaration order, Michael S. Tsirkin, 2022/11/05
- [PULL v3 19/81] tests/acpi: allow changes for core_count2 test, Michael S. Tsirkin, 2022/11/05
- [PULL v3 24/81] acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A, Michael S. Tsirkin, 2022/11/05
- [PULL v3 27/81] hw/mem/cxl-type3: Add MSIX support,
Michael S. Tsirkin <=
- [PULL v3 25/81] tests/acpi: virt: update ACPI MADT and FADT binaries, Michael S. Tsirkin, 2022/11/05
- [PULL v3 31/81] hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus, Michael S. Tsirkin, 2022/11/05
- [PULL v3 34/81] virtio: introduce virtio_queue_enable(), Michael S. Tsirkin, 2022/11/05
- [PULL v3 33/81] virtio: introduce virtio_queue_reset(), Michael S. Tsirkin, 2022/11/05
- [PULL v3 32/81] virtio: introduce __virtio_queue_reset(), Michael S. Tsirkin, 2022/11/05
- [PULL v3 49/81] acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors, Michael S. Tsirkin, 2022/11/05