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[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
From: |
Peter Maydell |
Subject: |
[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers |
Date: |
Fri, 30 Sep 2022 14:35:06 +0100 |
From: Francisco Iglesias <francisco.iglesias@amd.com>
Connect ZynqMP's USB controllers.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-zynqmp.h | 3 +++
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 85fd9f53daa..20bdf894aa0 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -42,6 +42,7 @@
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
#include "hw/timer/cadence_ttc.h"
+#include "hw/usb/hcd-dwc3.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -56,6 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_NUM_SPIS 2
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
+#define XLNX_ZYNQMP_NUM_USB 2
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@@ -132,6 +134,7 @@ struct XlnxZynqMPState {
XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 383e177a001..335cfc417d7 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -143,6 +143,14 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
77, 78, 79, 80, 81, 82, 83, 84
};
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
+ 0xFE200000, 0xFE300000
+};
+
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
+ 65, 70
+};
+
typedef struct XlnxZynqMPGICRegion {
int region_index;
uint32_t address;
@@ -428,6 +436,10 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
object_initialize_child(obj, "qspi-irq-orgate",
&s->qspi_irq_orgate, TYPE_OR_IRQ);
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
+ }
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -814,6 +826,30 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
object_property_add_alias(OBJECT(s), bus_name,
OBJECT(&s->qspi), target_bus);
}
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
+ OBJECT(system_memory), errp)) {
+ return;
+ }
+
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
+ gic_spi[usb_intr[i]]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
+ gic_spi[usb_intr[i] + 1]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
+ gic_spi[usb_intr[i] + 2]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
+ gic_spi[usb_intr[i] + 3]);
+ }
}
static Property xlnx_zynqmp_props[] = {
--
2.25.1
- [PULL 00/10] target-arm queue, Peter Maydell, 2022/09/30
- [PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO, Peter Maydell, 2022/09/30
- [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together, Peter Maydell, 2022/09/30
- [PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers,
Peter Maydell <=
- [PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node, Peter Maydell, 2022/09/30
- [PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI, Peter Maydell, 2022/09/30
- [PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node, Peter Maydell, 2022/09/30
- [PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node, Peter Maydell, 2022/09/30
- [PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP, Peter Maydell, 2022/09/30
- [PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls, Peter Maydell, 2022/09/30
- [PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD, Peter Maydell, 2022/09/30