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[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
From: |
Peter Maydell |
Subject: |
[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD |
Date: |
Fri, 30 Sep 2022 14:35:04 +0100 |
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
by the current architecture. In particular in commit 0b42f4fab9d3 we
forgot to add SCCD, which meant that an AArch32 guest couldn't
actually use the SCCD bit to disable counting in Secure state.
Add all the currently defined bits; we don't implement all of them,
but this makes them be reads-as-written, which is architecturally
valid and matches how we currently handle most of the others in the
mask.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
---
target/arm/cpu.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 33cdbc0143e..429ed42eece 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1334,11 +1334,15 @@ FIELD(CPTR_EL3, TTA, 20, 1)
FIELD(CPTR_EL3, TAM, 30, 1)
FIELD(CPTR_EL3, TCPAC, 31, 1)
+#define MDCR_MTPME (1U << 28)
+#define MDCR_TDCC (1U << 27)
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
#define MDCR_EPMAD (1U << 21)
#define MDCR_EDAD (1U << 20)
+#define MDCR_TTRF (1U << 19)
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
#define MDCR_SDD (1U << 16)
@@ -1353,7 +1357,9 @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
#define MDCR_HPMN (0x1fU)
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
#define CPSR_M (0x1fU)
#define CPSR_T (1U << 5)
--
2.25.1
- [PULL 00/10] target-arm queue, Peter Maydell, 2022/09/30
- [PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO, Peter Maydell, 2022/09/30
- [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together, Peter Maydell, 2022/09/30
- [PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers, Peter Maydell, 2022/09/30
- [PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node, Peter Maydell, 2022/09/30
- [PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI, Peter Maydell, 2022/09/30
- [PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node, Peter Maydell, 2022/09/30
- [PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node, Peter Maydell, 2022/09/30
- [PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP, Peter Maydell, 2022/09/30
- [PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls, Peter Maydell, 2022/09/30
- [PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD,
Peter Maydell <=