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[PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
From: |
Alistair Francis |
Subject: |
[PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState |
Date: |
Fri, 23 Sep 2022 14:07:04 +1000 |
From: Bernhard Beschow <shentey@gmail.com>
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
inherit from TYPE_MACHINE. This is an inconsistency which can cause
undefined behavior such as memory corruption.
Change SiFiveEState to inherit from MachineState since it is registered
as a machine.
Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220922075232.33653-1-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_e.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 83604da805..d738745925 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/gpio/sifive_gpio.h"
+#include "hw/boards.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \
@@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
typedef struct SiFiveEState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
SiFiveESoCState soc;
--
2.37.3
- [PULL 03/12] docs/system: clean up code escape for riscv virt platform, (continued)
- [PULL 03/12] docs/system: clean up code escape for riscv virt platform, Alistair Francis, 2022/09/23
- [PULL 04/12] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/23
- [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/23
- [PULL 02/12] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/23
- [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/23
- [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/23
- [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/23
- [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/23
- [PULL 08/12] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/23
- [PULL 09/12] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/23
- [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState,
Alistair Francis <=
- Re: [PULL 00/12] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/26