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[PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size
From: |
BALATON Zoltan |
Subject: |
[PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size |
Date: |
Tue, 13 Sep 2022 21:52:44 +0200 (CEST) |
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_sdram.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index bc28d69a26..242e2f4c6e 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -34,7 +34,6 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h" /* get_system_memory() */
-#include "exec/cpu-defs.h" /* target_ulong */
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@@ -122,11 +121,6 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
/*****************************************************************************/
/* DDR SDRAM controller */
-/*
- * XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing hwaddr, target_ulong
- * and uint32_t
- */
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -170,9 +164,9 @@ static inline hwaddr sdram_ddr_base(uint32_t bcr)
return bcr & 0xFF800000;
}
-static target_ulong sdram_ddr_size(uint32_t bcr)
+static hwaddr sdram_ddr_size(uint32_t bcr)
{
- target_ulong size;
+ hwaddr size;
int sh;
sh = (bcr >> 17) & 0x7;
@@ -513,9 +507,9 @@ static inline hwaddr sdram_ddr2_base(uint32_t bcr)
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_ddr2_size(uint32_t bcr)
+static hwaddr sdram_ddr2_size(uint32_t bcr)
{
- uint64_t size;
+ hwaddr size;
int sh;
sh = 1024 - ((bcr >> 6) & 0x3ff);
--
2.30.4
- [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse, (continued)
- [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse, BALATON Zoltan, 2022/09/13
- [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM, BALATON Zoltan, 2022/09/13
- [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility, BALATON Zoltan, 2022/09/13
- [PATCH v3 11/20] ppc440_sdram: Get rid of the init RAM hack, BALATON Zoltan, 2022/09/13
- [PATCH v3 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init, BALATON Zoltan, 2022/09/13
- [PATCH v3 13/20] ppc4xx_sdram: Rename functions to prevent name clashes, BALATON Zoltan, 2022/09/13
- [PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size,
BALATON Zoltan <=
- [PATCH v3 18/20] ppc4xx_sdram: Rename local state variable for brevity, BALATON Zoltan, 2022/09/13
- [PATCH v3 15/20] ppc440_sdram: QOM'ify, BALATON Zoltan, 2022/09/13
- [PATCH v3 16/20] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together, BALATON Zoltan, 2022/09/13
- [PATCH v3 19/20] ppc4xx_sdram: Generalise bank setup, BALATON Zoltan, 2022/09/13
- [PATCH v3 20/20] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling, BALATON Zoltan, 2022/09/13
- Re: [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups, Cédric Le Goater, 2022/09/14