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[PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shi
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From: |
Alistair Francis |
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Subject: |
[PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions |
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Date: |
Wed, 7 Sep 2022 10:03:27 +0200 |
From: "Yueh-Ting (eop) Chen" <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-4@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 7 +++++++
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6be3c4e739..d1daa764b7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1298,10 +1298,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t esz = sizeof(TS1); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1339,10 +1342,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
uint32_t total_elems = \
vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 07d86551a9..83b85bb851 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1901,6 +1901,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
--
2.37.2
- [PULL 09/44] target/riscv: Add check for csrs existed with U extension, (continued)
- [PULL 09/44] target/riscv: Add check for csrs existed with U extension, Alistair Francis, 2022/09/07
- [PULL 10/44] target/riscv: Fix checks in hmode/hmode32, Alistair Francis, 2022/09/07
- [PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1, Alistair Francis, 2022/09/07
- [PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Alistair Francis, 2022/09/07
- [PULL 11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions, Alistair Francis, 2022/09/07
- [PULL 14/44] docs: List kvm as a supported accelerator on RISC-V, Alistair Francis, 2022/09/07
- [PULL 16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Alistair Francis, 2022/09/07
- [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions, Alistair Francis, 2022/09/07
- [PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, Alistair Francis, 2022/09/07
- [PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions,
Alistair Francis <=
- [PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, Alistair Francis, 2022/09/07
- [PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/09/07
- [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions, Alistair Francis, 2022/09/07
- [PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions, Alistair Francis, 2022/09/07
- [PULL 25/44] target/riscv: Add Zihintpause support, Alistair Francis, 2022/09/07
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Alistair Francis, 2022/09/07
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals, Alistair Francis, 2022/09/07
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07