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[PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions
From: |
Alistair Francis |
Subject: |
[PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions |
Date: |
Wed, 7 Sep 2022 10:03:24 +0200 |
From: "Yueh-Ting (eop) Chen" <eop.chen@sifive.com>
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/internals.h | 5 +++--
target/riscv/cpu_helper.c | 2 ++
target/riscv/translate.c | 2 ++
target/riscv/vector_helper.c | 8 ++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
6 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ffb1a18873..561d7fa92c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -439,6 +439,7 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zmmul;
bool rvv_ta_all_1s;
+ bool rvv_ma_all_1s;
uint32_t mvendorid;
uint64_t marchid;
@@ -596,6 +597,7 @@ FIELD(TB_FLAGS, XL, 20, 2)
FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
FIELD(TB_FLAGS, VTA, 24, 1)
+FIELD(TB_FLAGS, VMA, 25, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 193ce57a6d..5620fbffb6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -26,8 +26,9 @@ FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
FIELD(VDATA, VTA, 4, 1)
FIELD(VDATA, VTA_ALL_1S, 5, 1)
-FIELD(VDATA, NF, 6, 4)
-FIELD(VDATA, WD, 6, 1)
+FIELD(VDATA, VMA, 6, 1)
+FIELD(VDATA, NF, 7, 4)
+FIELD(VDATA, WD, 7, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87daf7220f..650574accf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,6 +68,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
flags = FIELD_DP32(flags, TB_FLAGS, VTA,
FIELD_EX64(env->vtype, VTYPE, VTA));
+ flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+ FIELD_EX64(env->vtype, VTYPE, VMA));
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 76da8db8a7..8925a44c6e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -95,6 +95,7 @@ typedef struct DisasContext {
int8_t lmul;
uint8_t sew;
uint8_t vta;
+ uint8_t vma;
bool cfg_vta_all_1s;
target_ulong vstart;
bool vl_eq_vlmax;
@@ -1121,6 +1122,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
+ ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart = env->vstart;
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a96fc49c71..de895050e0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VTA);
}
+static inline uint32_t vext_vma(uint32_t desc)
+{
+ return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
static inline uint32_t vext_vta_all_1s(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
@@ -812,10 +817,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1,
void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, vs1, vs2, i);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c091824b6..5ec113f6fd 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1247,6 +1247,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn
*gvec_fn,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8,
@@ -1545,6 +1546,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
@@ -1627,6 +1629,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
--
2.37.2
- [PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V, (continued)
- [PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V, Alistair Francis, 2022/09/07
- [PULL 05/44] hw/riscv: virt: pass random seed to fdt, Alistair Francis, 2022/09/07
- [PULL 02/44] target/riscv: Force disable extensions if priv spec version does not match, Alistair Francis, 2022/09/07
- [PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table, Alistair Francis, 2022/09/07
- [PULL 07/44] target/riscv: H extension depends on I extension, Alistair Francis, 2022/09/07
- [PULL 09/44] target/riscv: Add check for csrs existed with U extension, Alistair Francis, 2022/09/07
- [PULL 10/44] target/riscv: Fix checks in hmode/hmode32, Alistair Francis, 2022/09/07
- [PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1, Alistair Francis, 2022/09/07
- [PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Alistair Francis, 2022/09/07
- [PULL 11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions,
Alistair Francis <=
- [PULL 14/44] docs: List kvm as a supported accelerator on RISC-V, Alistair Francis, 2022/09/07
- [PULL 16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Alistair Francis, 2022/09/07
- [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions, Alistair Francis, 2022/09/07
- [PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, Alistair Francis, 2022/09/07
- [PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, Alistair Francis, 2022/09/07
- [PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, Alistair Francis, 2022/09/07
- [PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/09/07
- [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions, Alistair Francis, 2022/09/07
- [PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions, Alistair Francis, 2022/09/07
- [PULL 25/44] target/riscv: Add Zihintpause support, Alistair Francis, 2022/09/07