[PULL 00/44] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80:

  Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into 
staging (2022-09-06 08:31:24 -0400)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220907

for you to fetch changes up to f0551560b5c01b1dcbed1ac46ca0bd1155330f5f:

  target/riscv: Update the privilege field for sscofpmf CSRs (2022-09-07 
09:19:15 +0200)

----------------------------------------------------------------
First RISC-V PR for QEMU 7.2

* Update [m|h]tinst CSR in interrupt handling
* Force disable extensions if priv spec version does not match
* fix shifts shamt value for rv128c
* move zmmul out of the experimental
* virt: pass random seed to fdt
* Add checks for supported extension combinations
* Upgrade OpenSBI to v1.1
* Fix typo and restore Pointer Masking functionality for RISC-V
* Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension
* Add Zihintpause support
* opentitan: bump opentitan version
* microchip_pfsoc: fix kernel panics due to missing peripherals
* Remove additional priv version check for mcountinhibit
* virt machine device tree improvements
* Add xicondops in ISA entry
* Use official extension names for AIA CSRs

----------------------------------------------------------------
Alexey Baturo (1):
      target/riscv: Fix typo and restore Pointer Masking functionality for 
RISC-V

Anup Patel (3):
      target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
      target/riscv: Force disable extensions if priv spec version does not match
      target/riscv: Use official extension names for AIA CSRs

Atish Patra (9):
      target/riscv: Remove additional priv version check for mcountinhibit
      hw/intc: Move mtimer/mtimecmp to aclint
      target/riscv: Add stimecmp support
      target/riscv: Add vstimecmp support
      target/riscv: Add sscofpmf extension support
      target/riscv: Simplify counter predicate function
      target/riscv: Add few cache related PMU events
      hw/riscv: virt: Add PMU DT node to the device tree
      target/riscv: Update the privilege field for sscofpmf CSRs

Bin Meng (2):
      roms/opensbi: Upgrade from v1.0 to v1.1
      docs: List kvm as a supported accelerator on RISC-V

Conor Dooley (5):
      hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
      hw/riscv: virt: fix uart node name
      hw/riscv: virt: fix the plic's address cells
      hw/riscv: virt: fix syscon subnode paths
      hw/core: fix platform bus node name

Daniel Henrique Barboza (1):
      hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

Dao Lu (1):
      target/riscv: Add Zihintpause support

Frédéric Pétrot (1):
      target/riscv: fix shifts shamt value for rv128c

Jason A. Donenfeld (1):
      hw/riscv: virt: pass random seed to fdt

Rahul Pathak (1):
      target/riscv: Add xicondops in ISA entry

Weiwei Li (8):
      target/riscv: move zmmul out of the experimental properties
      target/riscv: Add check for supported privilege mode combinations
      target/riscv: H extension depends on I extension
      target/riscv: Fix checkpatch warning may triggered in csr_ops table
      target/riscv: Add check for csrs existed with U extension
      target/riscv: Fix checks in hmode/hmode32
      target/riscv: Simplify the check in hmode to reuse the check in 
riscv_csrrw_check
      target/riscv: Fix priority of csr related check in riscv_csrrw_check

Wilfred Mallawa (1):
      hw/riscv: opentitan: bump opentitan version

Yueh-Ting (eop) Chen (9):
      target/riscv: rvv: Add mask agnostic for vv instructions
      target/riscv: rvv: Add mask agnostic for vector load / store instructions
      target/riscv: rvv: Add mask agnostic for vx instructions
      target/riscv: rvv: Add mask agnostic for vector integer shift instructions
      target/riscv: rvv: Add mask agnostic for vector integer comparison 
instructions
      target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic 
instructions
      target/riscv: rvv: Add mask agnostic for vector floating-point 
instructions
      target/riscv: rvv: Add mask agnostic for vector mask instructions
      target/riscv: rvv: Add mask agnostic for vector permutation instructions

eopXD (1):
      target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask 
agnostic behavior

 docs/about/build-platforms.rst                 |    2 +-
 include/hw/intc/riscv_aclint.h                 |    2 +
 include/hw/riscv/boot.h                        |    2 +-
 include/hw/riscv/microchip_pfsoc.h             |   14 +-
 include/hw/riscv/opentitan.h                   |   11 +-
 include/hw/riscv/virt.h                        |    1 +
 include/hw/timer/ibex_timer.h                  |    2 +
 target/riscv/cpu.h                             |   48 +-
 target/riscv/cpu_bits.h                        |   63 ++
 target/riscv/instmap.h                         |   45 +
 target/riscv/internals.h                       |    5 +-
 target/riscv/pmu.h                             |    8 +
 target/riscv/time_helper.h                     |   30 +
 target/riscv/insn16.decode                     |    7 +-
 target/riscv/insn32.decode                     |    7 +-
 disas/riscv.c                                  |   27 +-
 hw/core/sysbus-fdt.c                           |    2 +-
 hw/intc/riscv_aclint.c                         |   48 +-
 hw/intc/riscv_imsic.c                          |    4 +-
 hw/riscv/boot.c                                |    4 +-
 hw/riscv/microchip_pfsoc.c                     |   69 +-
 hw/riscv/opentitan.c                           |   12 +-
 hw/riscv/shakti_c.c                            |    3 +-
 hw/riscv/spike.c                               |    2 +-
 hw/riscv/virt.c                                |   45 +-
 hw/timer/ibex_timer.c                          |   18 +-
 target/riscv/cpu.c                             |  204 +++--
 target/riscv/cpu_helper.c                      |  293 ++++++-
 target/riscv/csr.c                             | 1038 +++++++++++++++---------
 target/riscv/machine.c                         |    8 +-
 target/riscv/pmu.c                             |  425 +++++++++-
 target/riscv/time_helper.c                     |  114 +++
 target/riscv/translate.c                       |   24 +-
 target/riscv/vector_helper.c                   |  152 +++-
 target/riscv/insn_trans/trans_rvi.c.inc        |   16 +
 target/riscv/insn_trans/trans_rvv.c.inc        |   28 +
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin |  Bin 108504 -> 117704 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin |  Bin 105296 -> 115344 bytes
 roms/opensbi                                   |    2 +-
 target/riscv/meson.build                       |    3 +-
 40 files changed, 2229 insertions(+), 559 deletions(-)
 create mode 100644 target/riscv/time_helper.h
 create mode 100644 target/riscv/time_helper.c