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[PULL 06/44] target/riscv: Add check for supported privilege mode combin
From: |
Alistair Francis |
Subject: |
[PULL 06/44] target/riscv: Add check for supported privilege mode combinations |
Date: |
Wed, 7 Sep 2022 10:03:15 +0200 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a3e4e2477f..b919ad9056 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -721,6 +721,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+ error_setg(errp,
+ "Setting S extension without U extension is illegal");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.37.2
- [PULL 00/44] riscv-to-apply queue, Alistair Francis, 2022/09/07
- [PULL 04/44] target/riscv: move zmmul out of the experimental properties, Alistair Francis, 2022/09/07
- [PULL 06/44] target/riscv: Add check for supported privilege mode combinations,
Alistair Francis <=
- [PULL 03/44] target/riscv: fix shifts shamt value for rv128c, Alistair Francis, 2022/09/07
- [PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V, Alistair Francis, 2022/09/07
- [PULL 05/44] hw/riscv: virt: pass random seed to fdt, Alistair Francis, 2022/09/07
- [PULL 02/44] target/riscv: Force disable extensions if priv spec version does not match, Alistair Francis, 2022/09/07
- [PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table, Alistair Francis, 2022/09/07
- [PULL 07/44] target/riscv: H extension depends on I extension, Alistair Francis, 2022/09/07
- [PULL 09/44] target/riscv: Add check for csrs existed with U extension, Alistair Francis, 2022/09/07
- [PULL 10/44] target/riscv: Fix checks in hmode/hmode32, Alistair Francis, 2022/09/07
- [PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1, Alistair Francis, 2022/09/07
- [PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Alistair Francis, 2022/09/07