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Re: [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_


From: Joao Martins
Subject: Re: [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end()
Date: Mon, 18 Jul 2022 14:55:45 +0100

On 7/18/22 13:58, Igor Mammedov wrote:
> On Fri, 15 Jul 2022 18:16:24 +0100
> Joao Martins <joao.m.martins@oracle.com> wrote:
> 
>> Remove pc_get_cxl_range_end() dependency on the CXL memory region,
>> and replace with one that does not require the CXL host_mr to determine
>> the start of CXL start.
>>
>> This in preparation to allow pc_pci_hole64_start() to be called early
>> in pc_memory_init(), handle CXL memory region end when its underlying
>> memory region isn't yet initialized.
>>
>> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
>> Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
>> ---
>>  hw/i386/pc.c | 18 ++++++++----------
>>  1 file changed, 8 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 3fdcab4bb4f3..c654be6cf0bd 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -843,17 +843,15 @@ static uint64_t pc_get_cxl_range_start(PCMachineState 
>> *pcms)
>>  
>>  static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
>>  {
>> -    uint64_t start = 0;
>> +    uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
>                                                      ^^^^^
> why it's here?
> 
MiB is the size of CXL region

It's essentially logic inherited by pc_memory_init() that got replaced by
cxl_range_start():

@@ -946,15 +962,7 @@ void pc_memory_init(PCMachineState *pcms,
         MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
         hwaddr cxl_size = MiB;
         ^^^^^^^^^^^^^^^^^^^^^^

-        if (pcmc->has_reserved_memory && machine->device_memory->base) {
-            cxl_base = machine->device_memory->base
-                + memory_region_size(&machine->device_memory->mr);
-        } else if (pcms->sgx_epc.size != 0) {
-            cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc);
-        } else {
-            cxl_base = pc_above_4g_end(pcms);
-        }
-
+        cxl_base = pc_get_cxl_range_start(pcms);



>>  
>> -    if (pcms->cxl_devices_state.host_mr.addr) {
>> -        start = pcms->cxl_devices_state.host_mr.addr +
>> -            memory_region_size(&pcms->cxl_devices_state.host_mr);
>> -        if (pcms->cxl_devices_state.fixed_windows) {
>> -            GList *it;
>> -            for (it = pcms->cxl_devices_state.fixed_windows; it; it = 
>> it->next) {
>> -                CXLFixedWindow *fw = it->data;
>> -                start = fw->mr.addr + memory_region_size(&fw->mr);
>> -            }
>> +    if (pcms->cxl_devices_state.fixed_windows) {
>> +        GList *it;
>> +
>> +        start = ROUND_UP(start, 256 * MiB);
> 
> and also this unexplained alignment.
> 
It's part of what CXL fixed windows logic in pc_memory_init().
And the hunks I added is the same calculation.
Let me copy here below:

            cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
            for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) 
{
                CXLFixedWindow *fw = it->data;

                fw->base = cxl_fmw_base;
                memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
                                      "cxl-fixed-memory-region", fw->size);
                memory_region_add_subregion(system_memory, fw->base, &fw->mr);
                e820_add_entry(fw->base, fw->size, E820_RESERVED);
                cxl_fmw_base += fw->size;
                cxl_resv_end = cxl_fmw_base;
            }


>> +        for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) 
>> {
>> +            CXLFixedWindow *fw = it->data;
>> +            start += fw->size;
>>          }
>>      }
>>  
> 



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