[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 35/35] docs/system: riscv: Update description of CPU
From: |
Alistair Francis |
Subject: |
[PULL v2 35/35] docs/system: riscv: Update description of CPU |
Date: |
Wed, 16 Feb 2022 16:29:12 +1000 |
From: Yu Li <liyu.yukiteru@bytedance.com>
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..08ce3c4177 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -23,9 +23,9 @@ The ``virt`` machine supports the following devices:
* 1 generic PCIe host bridge
* The fw_cfg device that allows a guest to obtain data from QEMU
-Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
-can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
-enables the hypervisor extension for RV64.
+The hypervisor extension has been enabled for the default CPU, so virtual
+machines with hypervisor extension can simply be used without explicitly
+declaring.
Hardware configuration information
----------------------------------
--
2.34.1
- [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs, (continued)
- [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/16
- [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/16
- [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/16
- [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/16
- [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/16
- [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/16
- [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/16
- [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/16
- [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/16
- [PULL v2 32/35] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/16
- [PULL v2 35/35] docs/system: riscv: Update description of CPU,
Alistair Francis <=
- [PULL v2 33/35] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/16
- [PULL v2 34/35] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/16
- Re: [PULL v2 00/35] riscv-to-apply queue, Peter Maydell, 2022/02/16