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[PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when avai
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From: |
Alistair Francis |
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Subject: |
[PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available |
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Date: |
Wed, 16 Feb 2022 16:29:04 +1000 |
From: Anup Patel <anup.patel@wdc.com>
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-17-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2643c8bc37..e3068d6126 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -212,8 +212,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
- "riscv,cpu-intc");
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_AIA)) {
+ static const char * const compat[2] = {
+ "riscv,cpu-intc-aia", "riscv,cpu-intc"
+ };
+ qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
+ (char **)&compat, ARRAY_SIZE(compat));
+ } else {
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ }
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
--
2.34.1
- [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback, (continued)
- [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/16
- [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/16
- [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/16
- [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/16
- [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/16
- [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/16
- [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/16
- [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/16
- [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/16
- [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/16
- [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available,
Alistair Francis <=
- [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/16
- [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/16
- [PULL v2 32/35] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/16
- [PULL v2 35/35] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/16
- [PULL v2 33/35] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/16
- [PULL v2 34/35] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/16
- Re: [PULL v2 00/35] riscv-to-apply queue, Peter Maydell, 2022/02/16