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[PATCH 19/20] tcg/i386: Implement more logical operations for avx512
From: |
Richard Henderson |
Subject: |
[PATCH 19/20] tcg/i386: Implement more logical operations for avx512 |
Date: |
Sat, 18 Dec 2021 11:42:49 -0800 |
The general ternary logic operation can implement
NOT, ORC, NAND, NOR, EQV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 10 +++++-----
tcg/i386/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 841b1febab..433a632d6a 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -188,11 +188,11 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_v256 have_avx2
#define TCG_TARGET_HAS_andc_vec 1
-#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_nand_vec 0
-#define TCG_TARGET_HAS_nor_vec 0
-#define TCG_TARGET_HAS_eqv_vec 0
-#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_orc_vec have_avx512vl
+#define TCG_TARGET_HAS_nand_vec have_avx512vl
+#define TCG_TARGET_HAS_nor_vec have_avx512vl
+#define TCG_TARGET_HAS_eqv_vec have_avx512vl
+#define TCG_TARGET_HAS_not_vec have_avx512vl
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec have_avx512vl
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index f982b6e615..86c66f9522 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -447,6 +447,7 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
@@ -3004,6 +3005,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = vpshldi_insn[vece];
sub = args[3];
goto gen_simd_imm8;
+
+ case INDEX_op_not_vec:
+ insn = OPC_VPTERNLOGQ;
+ a2 = a1;
+ sub = 0x33; /* !B */
+ goto gen_simd_imm8;
+ case INDEX_op_nor_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x11; /* norCB */
+ goto gen_simd_imm8;
+ case INDEX_op_nand_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x77; /* nandCB */
+ goto gen_simd_imm8;
+ case INDEX_op_eqv_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x99; /* xnorCB */
+ goto gen_simd_imm8;
+ case INDEX_op_orc_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0xdd; /* orB!C */
+ goto gen_simd_imm8;
+
gen_simd_imm8:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3224,6 +3248,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_nand_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:
@@ -3256,6 +3284,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_abs_vec:
case INDEX_op_dup_vec:
+ case INDEX_op_not_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
@@ -3284,6 +3313,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_nand_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
+ case INDEX_op_not_vec:
return 1;
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
--
2.25.1
- [PATCH 06/20] tcg/i386: Add tcg_out_evex_opc, (continued)
- [PATCH 06/20] tcg/i386: Add tcg_out_evex_opc, Richard Henderson, 2021/12/18
- [PATCH 07/20] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv, Richard Henderson, 2021/12/18
- [PATCH 08/20] tcg/i386: Implement avx512 variable shifts, Richard Henderson, 2021/12/18
- [PATCH 09/20] tcg/i386: Implement avx512 scalar shift, Richard Henderson, 2021/12/18
- [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate, Richard Henderson, 2021/12/18
- [PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions, Richard Henderson, 2021/12/18
- [PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift, Richard Henderson, 2021/12/18
- [PATCH 12/20] tcg/i386: Implement avx512 variable rotate, Richard Henderson, 2021/12/18
- [PATCH 15/20] tcg/i386: Remove rotls_vec from tcg_target_op_def, Richard Henderson, 2021/12/18
- [PATCH 14/20] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2021/12/18
- [PATCH 19/20] tcg/i386: Implement more logical operations for avx512,
Richard Henderson <=
- [PATCH 17/20] tcg/i386: Implement avx512 min/max/abs, Richard Henderson, 2021/12/18
- [PATCH 18/20] tcg/i386: Implement avx512 multiply, Richard Henderson, 2021/12/18
- [PATCH 20/20] tcg/i386: Implement bitsel for avx512, Richard Henderson, 2021/12/18
- [PATCH 16/20] tcg/i386: Expand scalar rotate with avx512 insns, Richard Henderson, 2021/12/18