Re: [PATCH 6/6] target/arm: Implement FEAT_LPA2

[Richard Henderson]

On 12/14/21 6:57 AM, Alex Bennée wrote:
> > +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
> > +{
> > +    return sextract64(id->id_aa64mmfr0,
> > +                      R_ID_AA64MMFR0_TGRAN4_SHIFT,
> > +                      R_ID_AA64MMFR0_TGRAN4_LENGTH) >= 1;
>
> Is this correct - it shows:
>
>    0b1111 4KB granule not supported.

Yes, that's why the signed extract, so not supported comes out as -1.
See D13.1.3 "Principles of the ID scheme for fields in ID registers".


> (a little more reading later)
>
>    The ID_AA64MMFR0_EL1.TGran4_2, ID_AA64MMFR0_EL1.TGran16_2 and
>    ID_AA64MMFR0_EL1.TGran64_2 fields that identify the memory translation stage 
> 2 granule size, do not follow
>    the standard ID scheme. Software must treat these fields as follows:

Note that we're not testing the *_2 fields, which are *stage2* support, not stage1.  I did 
add a comment about assuming stage2 encodes the same value as stage1 (which is true for 
all supported cpus).



r~