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[PATCH 4/6] target/arm: Implement FEAT_LVA
From: |
Richard Henderson |
Subject: |
[PATCH 4/6] target/arm: Implement FEAT_LVA |
Date: |
Wed, 8 Dec 2021 15:11:52 -0800 |
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the inverse of the maximum virtual
address space size).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 5 +++++
target/arm/cpu64.c | 1 +
target/arm/helper.c | 8 +++++++-
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 7f38d33b8e..5f9c288b1a 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -11,7 +11,7 @@
#ifdef TARGET_AARCH64
# define TARGET_LONG_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 48
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
+# define TARGET_VIRT_ADDR_SPACE_BITS 52
#else
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 40
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e33f37b70a..3149000004 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4288,6 +4288,11 @@ static inline bool isar_feature_aa64_ccidx(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
}
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
+}
+
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 15245a60a8..f44ee643ef 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -755,6 +755,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LPA */
cpu->isar.id_aa64mmfr2 = t;
t = cpu->isar.id_aa64zfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 568914bd42..6a59975028 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11324,7 +11324,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
/* TODO: This code does not support shareability levels. */
if (aarch64) {
- int min_tsz = 16, max_tsz = 39; /* TODO: ARMv8.2-LVA */
+ int min_tsz = 16, max_tsz = 39;
int parange;
param = aa64_va_parameters(env, address, mmu_idx,
@@ -11334,6 +11334,12 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
max_tsz = 48 - param.using64k;
}
+ if (param.using64k) {
+ if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
+ min_tsz = 12;
+ }
+ }
+ /* TODO: FEAT_LPA2 */
/*
* If TxSZ is programmed to a value larger than the maximum,
--
2.25.1
- [PATCH for-7.0 0/6] target/arm: Implement LVA, LPA, LPA2 features, Richard Henderson, 2021/12/08
- [PATCH 2/6] target/arm: Move arm_pamax out of line, Richard Henderson, 2021/12/08
- [PATCH 1/6] target/arm: Fault on invalid TCR_ELx.TxSZ, Richard Henderson, 2021/12/08
- [PATCH 4/6] target/arm: Implement FEAT_LVA,
Richard Henderson <=
- [PATCH 3/6] target/arm: Honor TCR_ELx.{I}PS, Richard Henderson, 2021/12/08
- [PATCH 5/6] target/arm: Implement FEAT_LPA, Richard Henderson, 2021/12/08
- [PATCH 6/6] target/arm: Implement FEAT_LPA2, Richard Henderson, 2021/12/08
- Re: [PATCH for-7.0 0/6] target/arm: Implement LVA, LPA, LPA2 features, Alex Bennée, 2021/12/14