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Re: [PATCH v3 20/20] target/riscv: Enable uxl field write


From: Richard Henderson
Subject: Re: [PATCH v3 20/20] target/riscv: Enable uxl field write
Date: Thu, 11 Nov 2021 12:49:58 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/11/21 6:58 AM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
  target/riscv/csr.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8f8f170768..43eaa6c710 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, 
int csrno,
           * RV32: MPV and GVA are not in mstatus. The current plan is to
           * add them to mstatush. For now, we just don't support it.
           */
-        mask |= MSTATUS_MPV | MSTATUS_GVA;
+        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
      }
mstatus = (mstatus & ~mask) | (val & mask); if (riscv_cpu_mxl(env) == MXL_RV64) {
-        /* SXL and UXL fields are for now read only */
+        /* SXL fields are for now read only */
          mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
-        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
      }
      env->mstatus = mstatus;

Still missing the update for write_sstatus, which I think is simply an update to sstatus_v1_10_mask.


r~




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