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[PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE |
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Date: |
Thu, 11 Nov 2021 13:57:55 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b48c7c346c..5f35217f7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,7 +106,6 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.25.1
- Re: [PATCH v3 10/20] target/riscv: Calculate address according to XLEN, (continued)
- [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/11
- [PATCH v3 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/11
- [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE,
LIU Zhiwei <=
- [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- [PATCH v3 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11