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[PULL 08/54] target/ppc: Implement cnttzdm
From: |
David Gibson |
Subject: |
[PULL 08/54] target/ppc: Implement cnttzdm |
Date: |
Tue, 9 Nov 2021 16:51:18 +1100 |
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-9-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 28 ++++++++++++++++++----
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index eb3383c99c..ee8c90d520 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -125,6 +125,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
+CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index c9e9ae35df..d3dc0a474e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -415,7 +415,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
}
#if defined(TARGET_PPC64)
-static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
{
TCGv_i64 tmp;
TCGLabel *l1;
@@ -424,12 +424,20 @@ static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src,
TCGv_i64 mask)
l1 = gen_new_label();
tcg_gen_and_i64(tmp, src, mask);
- tcg_gen_clzi_i64(tmp, tmp, 64);
+ if (trail) {
+ tcg_gen_ctzi_i64(tmp, tmp, 64);
+ } else {
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+ }
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
tcg_gen_subfi_i64(tmp, 64, tmp);
- tcg_gen_shr_i64(tmp, mask, tmp);
+ if (trail) {
+ tcg_gen_shl_i64(tmp, mask, tmp);
+ } else {
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ }
tcg_gen_ctpop_i64(tmp, tmp);
gen_set_label(l1);
@@ -443,7 +451,19 @@ static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true);
#else
qemu_build_not_reached();
#endif
--
2.33.1
- [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, (continued)
- [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, David Gibson, 2021/11/09
- [PULL 01/54] target/ppc: introduce do_ea_calc, David Gibson, 2021/11/09
- [PULL 05/54] target/ppc: Move LQ and STQ to decodetree, David Gibson, 2021/11/09
- [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c, David Gibson, 2021/11/09
- [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c, David Gibson, 2021/11/09
- [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree, David Gibson, 2021/11/09
[PULL 08/54] target/ppc: Implement cnttzdm,
David Gibson <=
[PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128, David Gibson, 2021/11/09
[PULL 07/54] target/ppc: Implement cntlzdm, David Gibson, 2021/11/09
[PULL 14/54] target/ppc: Implement DCFFIXQQ, David Gibson, 2021/11/09
[PULL 17/54] target/ppc: Implement DCTFIXQQ, David Gibson, 2021/11/09
[PULL 10/54] target/ppc: Implement pextd instruction, David Gibson, 2021/11/09
[PULL 15/54] host-utils: Introduce mulu128, David Gibson, 2021/11/09
[PULL 06/54] target/ppc: Implement PLQ and PSTQ, David Gibson, 2021/11/09
[PULL 09/54] target/ppc: Implement pdepd instruction, David Gibson, 2021/11/09
[PULL 13/54] target/ppc: Introduce REQUIRE_FPU, David Gibson, 2021/11/09
[PULL 18/54] target/ppc: Do not update nip on DFP instructions, David Gibson, 2021/11/09