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[PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv
From: |
Richard Henderson |
Subject: |
[PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv |
Date: |
Tue, 2 Nov 2021 07:06:59 -0400 |
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..41718b695b 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -111,6 +111,32 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
+#else
+ /**
+ * record_sigsegv:
+ * @cpu: cpu context
+ * @addr: faulting guest address
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGSEGV with si_code set for @maperr,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide anything to the signal
+ * handler with anything besides the user context registers, and
+ * the siginfo_t, then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
+ * so that a "normal" cpu exception can be raised. In this case,
+ * the signal must be raised by the architecture cpu_loop.
+ */
+ void (*record_sigsegv)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
--
2.25.1
- [PULL 00/60] accel/tcg patch queue, Richard Henderson, 2021/11/02
- [PULL 01/60] accel/tcg: Split out adjust_signal_pc, Richard Henderson, 2021/11/02
- [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller, Richard Henderson, 2021/11/02
- [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop, Richard Henderson, 2021/11/02
- [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write, Richard Henderson, 2021/11/02
- [PULL 06/60] linux-user: Reorg handling for SIGSEGV, Richard Henderson, 2021/11/02
- [PULL 12/60] linux-user/host/aarch64: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 08/60] linux-user/host/ppc: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 17/60] linux-user/host/riscv: Improve host_signal_write, Richard Henderson, 2021/11/02
- [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv,
Richard Henderson <=
- [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill, Richard Henderson, 2021/11/02
- [PULL 30/60] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures, Richard Henderson, 2021/11/02
- [PULL 15/60] linux-user/host/riscv: Populate host_signal.h, Richard Henderson, 2021/11/02
- [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/11/02
- [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/11/02
- [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/02
- [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv, Richard Henderson, 2021/11/02